发明授权
- 专利标题: Data transferring circuit which aligns clock and data
- 专利标题(中): 数据传输电路对齐时钟和数据
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申请号: US347618申请日: 1994-11-30
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公开(公告)号: US5796795A公开(公告)日: 1998-08-18
- 发明人: Harry Edward Mussman , Hung-San Chen , Stephen P. Hartman
- 申请人: Harry Edward Mussman , Hung-San Chen , Stephen P. Hartman
- 申请人地址: MA Waltham
- 专利权人: GTE Laboratories Incorporated
- 当前专利权人: GTE Laboratories Incorporated
- 当前专利权人地址: MA Waltham
- 主分类号: H04J3/06
- IPC分类号: H04J3/06 ; H04L7/033 ; H04L25/36 ; H04L7/00 ; H04L25/40
摘要:
A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations.
公开/授权文献
- US4937404A Jack with a switch 公开/授权日:1990-06-26
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