发明授权
US5796977A Highly pipelined bus architecture 失效
高度流水线总线架构

Highly pipelined bus architecture
摘要:
A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
公开/授权文献
信息查询
0/0