发明授权
- 专利标题: Highly pipelined bus architecture
- 专利标题(中): 高度流水线总线架构
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申请号: US688238申请日: 1996-07-29
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公开(公告)号: US5796977A公开(公告)日: 1998-08-18
- 发明人: Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
- 申请人: Nitin V. Sarangdhar , Gurbir Singh , Konrad Lai , Stephen S. Pawlowski , Peter D. MacWilliams , Michael W. Rhodehamel
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G06F13/18 ; G06F12/00 ; G06F13/00
摘要:
A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.
公开/授权文献
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