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    Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
    1.
    再颁专利
    Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system 有权
    在流水线系统中有效处理延迟顺序相关的存储器访问事务的机制

    公开(公告)号：USRE40921E1

    公开(公告)日：2009-09-22

    申请号：US09972704

    申请日：2001-10-04

    申请人： William S. Wu ,  Peter D. MacWilliams ,  Stephen Pawlowski ,  Muthurajan Jayakumar

    发明人： William S. Wu ,  Peter D. MacWilliams ,  Stephen Pawlowski ,  Muthurajan Jayakumar

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1626

    摘要： A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

    摘要翻译： 如果交易无法按顺序完成，则总线代理人会延迟有序的交易。 当有序事务被延期时，如果可以保证有序事务和下一个有序事务的连续顺序，则其对下一个有序事务的可见性被断言。 该可见性指示允许总线代理继续下一个有序的事务，而不等待延迟事务的完成状态。 可见度指示提供有序交易的快速处理。

    Method and apparatus for implementing multiple memory buses on a memory module
    3.
    发明授权
    Method and apparatus for implementing multiple memory buses on a memory module 有权
    用于在存储器模块上实现多个存储器总线的方法和装置

    公开(公告)号：US06587912B2

    公开(公告)日：2003-07-01

    申请号：US09163860

    申请日：1998-09-30

    申请人： Michael W. Leddige ,  Bryce D. Horine ,  Randy Bonella ,  Peter D. MacWilliams

    发明人： Michael W. Leddige ,  Bryce D. Horine ,  Randy Bonella ,  Peter D. MacWilliams

    IPC分类号： G06F1200

    CPC分类号： G06F13/4256

    摘要： A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus.

    摘要翻译： 计算机系统存储器模块包括双向中继器集线器，其在第一方向上将第一端口中的存储器总线信号作为输入，再生存储器信号，并将第二端口处的再生存储器信号作为至少一个单独的 信号，用于耦合到存储器总线，用于每个再生的分离信号。 在第二方向上，双向中继器集线器将第二端口处的至少一个存储器总线信号作为输入，再生每个输入存储器总线信号，并在第一端口处输出再生的存储器信号以耦合到存储器总线。

    Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment
    4.
    发明授权
    Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment 失效
    用于在源同步环境中从非源同步组件捕获数据的方法和装置

    公开(公告)号：US06247136B1

    公开(公告)日：2001-06-12

    申请号：US09038682

    申请日：1998-03-09

    申请人： Peter D. MacWilliams ,  Harry Muljono ,  Thomas J. Mozdzen

    发明人： Peter D. MacWilliams ,  Harry Muljono ,  Thomas J. Mozdzen

    IPC分类号： G06F1300

    CPC分类号： G06F12/0802 ,  G06F13/4243

    摘要： A method and apparatus for communicating signals between a source synchronous component and a non-source synchronous component of a system is described. The present invention provides a strobe signal from the source synchronous component that is delayed and used to latch data received from a non-source synchronous component. The amount of delay provided is determined based on the timing of data request cycles to the non-source synchronous component. Thus, the present invention allows data to be received by a source synchronous component from a component that does not generate a strobe signal used for latching received data that would be generated by a source synchronous component.

    摘要翻译： 描述了用于在系统的源同步组件和非源同步组件之间传送信号的方法和装置。 本发明提供来自源同步分量的选通信号，其被延迟并用于锁存从非源同步分量接收的数据。 所提供的延迟量基于对非源同步分量的数据请求周期的定时来确定。 因此，本发明允许来自不产生用于锁存由源同步分量产生的接收数据的选通信号的分量的源同步分量的数据。

    Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
    6.
    发明授权
    Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system 失效
    用于在多处理系统中切换源同步和公共时钟数据传输模式的方法和装置

    公开(公告)号：US5919254A

    公开(公告)日：1999-07-06

    申请号：US881941

    申请日：1997-06-25

    申请人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  William S. Wu ,  Len J. Schultz

    发明人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  William S. Wu ,  Len J. Schultz

    IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F1/12 ,  G06F13/42

    CPC分类号： G06F13/385 ,  G06F13/4018 ,  G06F13/405

    摘要： A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.

    摘要翻译： 一种用于在包括以总线时钟速率工作的总线的计算机系统中的总线代理之间传送数据的方法和装置。 该方法包括从请求代理接收交易请求的步骤，包括请求代理处理的多个数据宽度的指示。 响应于交易请求，根据请求代理和响应代理进程的数据宽度配置数据传输。 如果数据宽度是第一多个数据宽度之一，则相对于总线时钟异步执行数据传输，否则，数据传输是相对于总线时钟同步执行的。

    Method and apparatus for changing data transfer widths in a computer system
    7.
    发明授权
    Method and apparatus for changing data transfer widths in a computer system 失效
    用于在计算机系统中改变数据传输宽度的方法和装置

    公开(公告)号：US5911053A

    公开(公告)日：1999-06-08

    申请号：US723572

    申请日：1996-09-30

    申请人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Gurbir Singh

    发明人： Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Gurbir Singh

    IPC分类号： G06F13/40 ,  G06F3/00

    CPC分类号： G06F13/4018

    摘要： In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.

    摘要翻译： 在用于改变计算机系统中的数据传输宽度的方法和装置中，总线上的第一代理向总线上的第二代理提供第一指示，以识别第一代理所支持的一个或多个数据传输宽度。 然后，第二代理向第一代理提供识别由第二代理支持的一个或多个数据传输宽度的第二指示。 然后基于第一指示和第二指示确定数据传输宽度。 根据本发明的实施例，参与交易的第三代理还能够向第一代理和/或第二代理提供第三指示，以识别由第三代理支持的一个或多个数据传输宽度。 然后基于第一，第二和第三指示确定数据传送宽度。

    Highly pipelined bus architecture
    8.
    发明授权
    Highly pipelined bus architecture 失效
    高度流水线总线架构

    公开(公告)号：US5796977A

    公开(公告)日：1998-08-18

    申请号：US688238

    申请日：1996-07-29

    申请人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

    发明人： Nitin V. Sarangdhar ,  Gurbir Singh ,  Konrad Lai ,  Stephen S. Pawlowski ,  Peter D. MacWilliams ,  Michael W. Rhodehamel

    IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/18 ,  G06F12/0831

    摘要： A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

    摘要翻译： 描述了包含维护数据一致性的流水线总线的计算机系统，支持长延迟事务并提供处理器顺序。 计算机系统包括总线代理，其具有在系统总线上跟踪多个未完成事务的按顺序队列，并且响应于在一个事务中提供窥探结果和修改的数据的事务请求来执行窥探。 此外，系统通过在用于重新启动延迟事务的事务请求期间提供延迟标识符来支持长延迟事务。

    Second level cache controller unit and system
    9.
    发明授权
    Second level cache controller unit and system 失效
    二级缓存控制器单元和系统

    公开(公告)号：US5355467A

    公开(公告)日：1994-10-11

    申请号：US208090

    申请日：1994-03-08

    申请人： Peter D. MacWilliams ,  Robert L. Farrell ,  Adalberto Golbert ,  Itzik Silas

    发明人： Peter D. MacWilliams ,  Robert L. Farrell ,  Adalberto Golbert ,  Itzik Silas

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F2212/6082

    摘要： A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

    摘要翻译： 实现为集成电路单元的第二级高速缓冲存储器控制器与辅助随机存取高速缓冲存储器和主存储器（系统）总线控制器一起操作以形成第二级高速缓存存储器子系统。 该子系统与本地处理器（CPU）总线和主存储器总线接口，由总线提供独立的访问，从而当CPU所需的数据位于二级缓存中时，减少主存储器总线的流量。 类似地，当主存储器总线的二级缓存访问被窃听并回写到主存储器时，CPU总线流量被最小化。 与主存储器总线连接的监听锁存器通过次级高速缓存控制器单元中的高速缓存目录提供对高速缓冲存储器的窥探访问。 控制器还支持使用最近使用（MRU）主存储器直写和流水线存储器总线周期请求的控制器标签阵列和二级缓存中的并行查找。

    Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit
    10.
    发明授权
    Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit 失效
    推挽串行总线耦合到多个具有冲突检测电路和仲裁电路的装置

    公开(公告)号：US4785396A

    公开(公告)日：1988-11-15

    申请号：US148763

    申请日：1988-01-26

    申请人： Sean T. Murphy ,  Narjala Bhasker ,  Peter D. MacWilliams ,  Stephen J. Packer

    发明人： Sean T. Murphy ,  Narjala Bhasker ,  Peter D. MacWilliams ,  Stephen J. Packer

    IPC分类号： H04L12/413 ,  G06F13/40 ,  G06F11/00

    CPC分类号： H04L12/413

    摘要： A high speed serial bus is disclosed have particular application for use in passing messages in a multiple processor computer system. The serial bus includes a three-wire serial link having lines identified as "SDA", "SDB" and "ground". The ground line provides a common reference for all devices coupled to the serial bus. A message controller is coupled to each agent for transmitting and receiving serial data along the bus. Both lines of the serial bus as well as the ground are coupled to a bus state detector in the message controller which provides three basic signal outputs. The bus state detector determines whether or not the bus is in use, a collision has occurred between messages, and decodes data received on the bus. Data which is transmitted along the serial bus is driven on lines SDA and SDB 180 degrees out of phase relative to each other. The message controller encodes messages to be transmitted using, in the present embodiment, well known Manchester encoding techniques. A bus idle state occurs when all transmitters are off allowing both lines SDA and SDB be pulled high by pull-up resistors. Valid data states may occur any time a single transmitter is transmitting. When two or more transmitters begin transmitting a collision state exists. The message controller recognizes collisions and provides a back-off algorithm.

    摘要翻译： 公开了一种高速串行总线具有用于在多处理器计算机系统中传递消息的特定应用。 串行总线包括具有被标识为“SDA”，“SDB”和“地”的线的三线串行链路。 地线为耦合到串行总线的所有设备提供了通用参考。 消息控制器耦合到每个代理，用于沿总线发送和接收串行数据。 串行总线和地线的两条线都耦合到提供三个基本信号输出的消息控制器中的总线状态检测器。 总线状态检测器确定总线是否在使用中，消息之间是否发生冲突，并且解码在总线上接收的数据。 沿着串行总线发送的数据在相互之间相差180度的线SDA和SDB上驱动。 消息控制器在本实施例中使用众所周知的曼彻斯特编码技术对要发送的消息进行编码。 当所有发送器关闭时，总线空闲状态发生，允许通过上拉电阻将SDA和SDB两个线拉高。 有效的数据状态可能在单个发射机发射时发生。 当两个或多个发射机开始发送时，存在冲突状态。 消息控制器识别冲突并提供退避算法。