A scheme for variable-delay instructions in a digital processor that allows for variable delay of some instructions to increase performance at different frequencies. The variable-delay (VD) feature allows flag-modifying instructions to execute in a differing number (1 or 2) of clock cycles, depending on the application. In applications that clock the processor at less than maximum frequency, instructions that modify the flag are executed in one clock cycle. In applications that clock the processor at its maximum frequency, the instructions that modify the flag are executed in two clock cycles. If the critical path, and consequently the maximum frequency, of a processor is determined by a flag-modifying operation immediately followed by a flag-reading operation, then the VD scheme helps increase performance at either frequency. The performance increase is proportional to the difference in delays between the critical path associated with flag-modifying and other critical paths. At the lower frequency, a given application consumes slightly less energy and the cost of implementing the scheme is minimal.