A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first and second different voltages during successive abutting activation periods. The first device supplies a current to the common terminal that is considerably greater than the current supplied to the common terminal by the second device. The arrangement further includes a third device for pulling the common terminal to the second voltage at all times. The third device supplies a current to the common terminal that is either equal to or less than the current supplied by the second device.