发明授权
US5812603A Digital receiver using a concatenated decoder with error and erasure
correction
失效
数字接收机使用带有错误和擦除校正的级联解码器
- 专利标题: Digital receiver using a concatenated decoder with error and erasure correction
- 专利标题(中): 数字接收机使用带有错误和擦除校正的级联解码器
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申请号: US701632申请日: 1996-08-22
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公开(公告)号: US5812603A公开(公告)日: 1998-09-22
- 发明人: Daniel A. Luthi , Ravi Bhaskaran , Dojun Rhee , Advait M. Mogre
- 申请人: Daniel A. Luthi , Ravi Bhaskaran , Dojun Rhee , Advait M. Mogre
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 主分类号: H04L1/00
- IPC分类号: H04L1/00 ; H04L25/34
摘要:
A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.
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