64/256 quadrature amplitude modulation trellis coded modulation decoder
    1.
    发明授权
    64/256 quadrature amplitude modulation trellis coded modulation decoder 失效
    64/256正交幅度调制网格编码调制解码器

    公开(公告)号:US06269129B1

    公开(公告)日:2001-07-31

    申请号:US09066048

    申请日:1998-04-24

    Abstract: A quadrature amplitude modulation (QAM) trellis coded modulation (TCM) decoder for decoding a stream of QAM TCM signals is disclosed. Each of the signals has a plurality of associated branch metrics and has an in-phase component and a quadrature component. The in-phase component is defined by a plurality of in-phase symbols and the quadrature component is defined by a plurality of quadrature symbols. The QAM TCM decoder includes a first Viterbi decoder and a second Viterbi decoder. The first Viterbi decoder is configured to receive an in-phase component of a QAM TCM signal for decoding the associated in-phase symbols into an in-phase decoded bit and a plurality of uncoded in-phase bits. The second Viterbi decoder configured to receive a quadrature component of the QAM TCM signal for decoding the associated quadrature symbols into a quadrature decoded bit and a plurality of uncoded quadrature bits. The first and second Viterbi decoders are adapted to decode 64- or 256-QAM TCM signals.

    Abstract translation: 公开了用于解码QAM TCM信号流的正交幅度调制(QAM)格状编码调制(TCM)解码器。 每个信号具有多个相关联的分支度量,并且具有同相分量和正交分量。 同相分量由多个同相符号定义,并且正交分量由多个正交符号定义。 QAM TCM解码器包括第一维特比解码器和第二维特比译码器。 第一维特比解码器被配置为接收QAM TCM信号的同相分量,用于将相关联的同相符号解码为同相解码位和多个未编码的同相位。 第二维特比解码器,被配置为接收QAM TCM信号的正交分量,用于将相关联的正交符号解码为正交解码比特和多个未编码正交比特。 第一和第二维特比解码器适于解码64或256-QAM TCM信号。

    Digital receiver using a concatenated decoder with error and erasure
correction
    2.
    发明授权
    Digital receiver using a concatenated decoder with error and erasure correction 失效
    数字接收机使用带有错误和擦除校正的级联解码器

    公开(公告)号:US5812603A

    公开(公告)日:1998-09-22

    申请号:US701632

    申请日:1996-08-22

    CPC classification number: H04L1/0057 H04L1/0045 H04L1/0065 H04L1/0071

    Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

    Abstract translation: 提出了一种用于检测突发错误并向块解码器提供擦除信息的通信接收机系统,从而以仅复杂度的最小增加有效地加倍了块解码器的传统校正能力。 在一个实施例中,该机制采用电路的形式,其对内部解码器的输出进行重新编码,将其与所接收的代码符号序列进行比较,并且当过多数量的代码标记内部解码器输出的一部分以进行擦除 检测到符号错误。 在第二实施例中,该机制采用对信道信号进行硬符号决定的电路的形式,将硬判决与信道信号进行比较以确定噪声电平,此后在具有过高噪声电平的区域中标记信道输出。

    System and method using polar coordinate representation for quantization and distance metric determination in an M-PSK demodulator
    3.
    发明授权
    System and method using polar coordinate representation for quantization and distance metric determination in an M-PSK demodulator 有权
    在M-PSK解调器中使用极坐标表示进行量化和距离度量确定的系统和方法

    公开(公告)号:US06421400B1

    公开(公告)日:2002-07-16

    申请号:US09244596

    申请日:1999-02-04

    CPC classification number: H04L1/006 H04L1/0054 H04L27/186

    Abstract: A digital communications receiver is provided with a PSK demodulator and a soft-decision decoder. The PSK demodulator is configured to accept a receive signal and responsively produce quantized baseband signal components which include a quantized radial component RQ and a quantized angular component &thgr;Q. The soft-decision decoder is coupled to the PSK demodulator to receive the quantized baseband signal components and is configured to convert the quantized signal components into decoded information bits. The soft-decision decoder preferably uses a squared Euclidean distance metric calculation for the decoding process. Using polar coordinate quantization provides an improved performance relative to Cartesian coordinate quantization. A new distance metric for TCM decoding is also provided which requires less implementation complexity than a standards Euclidean distance metric calculation, and which suffers no significant performance loss.

    Abstract translation: 数字通信接收机具有PSK解调器和软判决解码器。 PSK解调器被配置为接受接收信号并且响应地产生量化的基带信号分量,其包括量化的径向分量RQ和量化的角分量θQ。 软判决解码器耦合到PSK解调器以接收量化的基带信号分量,并且被配置为将量化的信号分量转换成解码的信息比特。 软判决解码器优选地使用用于解码处理的平方欧几里得距离度量计算。 使用极坐标量化提供了相对于笛卡尔坐标量化的改进的性能。 还提供了用于TCM解码的新的距离度量,其比欧标距离度量标准计算要求更少的实现复杂度,并且其没有显着的性能损失。

    Digital receiver using equalization and block decoding with erasure and
error correction
    4.
    发明授权
    Digital receiver using equalization and block decoding with erasure and error correction 失效
    数字接收机使用均衡和块解码,具有擦除和纠错

    公开(公告)号:US5708665A

    公开(公告)日:1998-01-13

    申请号:US701710

    申请日:1996-08-22

    CPC classification number: H04L1/0057 H04L1/0045 H04L1/0065 H04L1/208

    Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

    Abstract translation: 提供了一种用于检测突发错误并向块解码器(外部解码器)提供擦除信息的通信接收机系统,从而仅以最小的复杂度增加来有效地加倍了块解码器的常规校正能力。 在一个实施例中,该机制采用电路的形式,其对内部解码器的输出进行重新编码,将其与所接收的代码符号序列进行比较,并且当过多数量的代码标记内部解码器输出的一部分以进行擦除 检测到符号错误。 在第二实施例中,该机制采用对信道信号进行硬符号决定的电路的形式,将硬判决与信道信号进行比较以确定噪声电平,此后在具有过高噪声电平的区域中标记信道输出。

    Method and apparatus for decoding M-PSK turbo code using new approximation technique
    5.
    发明授权
    Method and apparatus for decoding M-PSK turbo code using new approximation technique 有权
    使用新的近似技术解码M-PSK turbo码的方法和装置

    公开(公告)号:US06807238B1

    公开(公告)日:2004-10-19

    申请号:US09773033

    申请日:2001-02-01

    Abstract: The method of the present invention decodes a received symbol that represents data bits including message bits and parity-check bits. The method comprises (a) mapping the symbol onto a received signal point in a signal space, the signal point having an in-phase component (I) and a quadrature phase component (Q) in the signal space; (b) computing reliability information for each data bit, the reliability information associated with a distance di={square root over ((I−Ii)2+(Q−Qi)2)} between the received signal point (I, Q) and a reference constellation point (Ii, Qi) in the signal space, where i=0, 1, . . . , M−1 (for M an integer), by replacing calculation of (I−Ii)2+(Q−Qi)2 with calculation of 2(Ii×I+Qi×Q); (c) decoding the received symbol using the reliability information and a priori information to produce estimated message bits, the a priori information having a predetermined value in a first decoding; (d) calculating difference between received message bits and the estimated message bits to produce extrinsic information of estimated message bits; and (e) repeating at least once the mapping, computing, decoding and calculating, using the extrinsic information produced in a preceding calculating as the a priori information.

    Abstract translation: 本发明的方法对包含消息位和奇偶校验位的数据位的接收符号进行解码。 该方法包括:(a)将符号映射到信号空间中的接收信号点,信号点在信号空间中具有同相分量(I)和正交相位分量(Q); (b)计算每个数据比特的可靠性信息,与接收信号点之间的距离di = {平方根超过((I-Ii)2>(Q-Qi)2)相关联的可靠性信息} I,Q)和信号空间中的参考星座点(Ii,Qi),其中i = 0,1,。 。 。 通过用2(IixI + QixQ)的计算代替(I-Ii)2 +(Q-Qi)2的计算,M-1(对于M为整数)。 (c)使用所述可靠性信息和先验信息来解码所接收的符号以产生估计的消息比特,所述先验信息在第一解码中具有预定值; (d)计算接收到的消息比特与所估计的消息比特之间的差异,以产生估计消息比特的外在信息; 以及(e)使用先前计算中产生的外在信息作为先验信息,重复至少一次映射,计算,解码和计算。

    Recursive decoder architecture for binary block codes
    6.
    发明授权
    Recursive decoder architecture for binary block codes 失效
    二进制块代码的递归解码器架构

    公开(公告)号:US06349117B1

    公开(公告)日:2002-02-19

    申请号:US09088429

    申请日:1998-06-01

    Applicant: Dojun Rhee

    Inventor: Dojun Rhee

    CPC classification number: H03M13/3944 H03M13/136 H03M13/6561

    Abstract: A recursive decoder for decoding a binary codeword of length N having a first stage, at least one intermediate stage, and a final stage. The first stage including a plurality of decoder groups, each of the groups having a plurality of sets of first and second decoders, each of the first and second decoders having a plurality of inputs and an output, a plurality of adder groups, each of the adders having a first input connected to the output of the first decoder of one of the sets and a second input connected to the output of the second decoder of one of the sets, and an output. The at least one intermediate stage including at least one decoder group, each of the at least one decoder group having a plurality of sets of first and second comparators, each of the first and second comparators having inputs and an output, the inputs of each of the comparators in a first intermediate stage connected to the outputs of one of the plurality of adder groups, at least one adder group, each of the adders having a first input connected to the output of the first comparator of one of the sets and a second input connected to the output of the second comparator of one of the sets, and an output, the inputs of each of the comparators in other than the first intermediate stage connected to the outputs of one of at least one adder group. The final stage, including a comparator having inputs and an output, the inputs connected to the outputs of a final intermediate stage.

    Abstract translation: 一种用于解码具有第一级,至少一个中间级和最后级的长度为N的二进制码字的递归解码器。 第一级包括多个解码器组,每个组具有多组第一和第二解码器,第一和第二解码器中的每一个具有多个输入和输出,多个加法器组,每个 具有连接到所述组中的一个的第一解码器的输出的第一输入和连接到所述组中的一个的第二解码器的输出的第二输入的加法器和输出。 所述至少一个中间级包括至少一个解码器组,所述至少一个解码器组中的每一个具有多组第一和第二比较器,所述第一和第二比较器中的每一个具有输入和输出, 连接到所述多个加法器组之一的输出的第一中间级中的比较器,至少一个加法器组,每个加法器具有连接到所述组中的一组的第一比较器的输出的第一输入端和第二输入端 连接到所述组中的一组的第二比较器的输出的输入,以及输出,连接到至少一个加法器组之一的输出的除第一中间级之外的每个比较器的输入。 最后阶段,包括具有输入和输出的比较器,输入连接到最终中间级的输出。

    Apparatus and method for recovering information bits from a 64/256-quadrature amplitude modulation treliss coded modulation decoder
    7.
    发明授权
    Apparatus and method for recovering information bits from a 64/256-quadrature amplitude modulation treliss coded modulation decoder 失效
    用于从64/256正交幅度调制格雷利编码调制解码器恢复信息比特的装置和方法

    公开(公告)号:US06233712B1

    公开(公告)日:2001-05-15

    申请号:US09065751

    申请日:1998-04-24

    Abstract: An apparatus for recovering information bits from in-phase and quadrature components of a stream of quadrature amplitude modulation (QAM) trellis code modulation (TCM) signals is disclosed. Each signal has an in-phase component and a quadrature component. The in-phase component includes a decoded bit and a plurality of uncoded in-phase bits and the quadrature component includes a decoded quadrature bit and a plurality of uncoded quadrature bits. The apparatus includes a reencode and puncturing circuitry, an inverse mapping circuitry, and a recovery circuitry. The reencode and puncture circuitry is adapted to receive the in-phase and quadrature components of a QAM TCM signal for encoding the decoded in-phase and quadrature bits. The reencode and puncture circuitry punctures the encoded in-phase bit with the uncoded in-phase bits to generate an in-phase component index. In addition, the reencode and puncture circuitry punctures the encoded quadrature bit with the remaining quadrature bits to generate a quadrature component index. The inverse mapping circuitry is coupled to the reencode and puncture circuitry to receive the in-phase component index and the quadrature component index for recovering a first set of in-phase bits and a second set of quadrature bits. The recovery circuitry is coupled to the inverse mapping circuitry to receive the first set of in-phase bits and the second set of quadrature bits. The recovery circuitry is also coupled to receive the decoded in-phase and quadrature bits. The recovery circuitry recovers a set of information bits by assembling the received bits.

    Abstract translation: 公开了一种用于从正交幅度调制(QAM)格码调制(TCM)信号流的同相和正交分量中恢复信息比特的装置。 每个信号具有同相分量和正交分量。 同相分量包括解码比特和多个未编码的同相位,并且正交分量包括解码的正交比特和多个未编码的正交比特。 该装置包括重新编码和打孔电路,反向映射电路和恢复电路。 重新编码和穿孔电路适于接收用于对解码的同相和正交位进行编码的QAM TCM信号的同相和正交分量。 重新编码和穿孔电路使用未编码的同相位比特对经编码的同相位位进行穿刺,以产生同相分量索引。 此外,重新编码和穿孔电路用剩余的正交比特对编码的正交比特进行穿刺,以产生正交分量索引。 逆映射电路耦合到重新编码和穿孔电路,以接收同相分量索引和正交分量索引,用于恢复第一组同相位和第二组正交位。 恢复电路耦合到逆映射电路以接收第一组同相位和第二组正交位。 恢复电路还耦合以接收解码的同相和正交位。 恢复电路通过组合接收到的位来恢复一组信息位。

    System to efficiently transmit two HDTV channels over satellite using turbo coded 8PSK modulation for DSS compliant receivers
    8.
    发明授权
    System to efficiently transmit two HDTV channels over satellite using turbo coded 8PSK modulation for DSS compliant receivers 有权
    系统通过卫星使用针对DSS兼容接收机的turbo编码8PSK调制来高效地传输两个HDTV频道

    公开(公告)号:US06987543B1

    公开(公告)日:2006-01-17

    申请号:US09726819

    申请日:2000-11-30

    Abstract: A channel encoding system and a channel decoding system for use in transmitting multiple high definition television programs in a single satellite channel. The channel encoding system may comprise a frame formatter that may be configured to format a transport stream to produce a block stream. An error correction encoder may be configured to encode the block stream to produce an error protected block stream. An interleave module may be configured to interleave the error protected block stream to produce a data stream. A turbo encoder may be configured to encode the data stream to produce an encoded stream. A bit-to-symbol mapper may be configured to map the encoded stream to produce a symbol stream capable of at least eight different symbols. Finally, a modulator may be configured to modulate the symbol stream.

    Abstract translation: 信道编码系统和用于在单个卫星信道中发送多个高清晰度电视节目的信道解码系统。 信道编码系统可以包括帧格式化器,其可以被配置为格式化传输流以产生块流。 纠错编码器可以被配置为对块流进行编码以产生错误保护的块流。 交织模块可以被配置为交错错误保护块流以产生数据流。 turbo编码器可以被配置为对数据流进行编码以产生编码的流。 位对符号映射器可以被配置为映射编码流以产生能够具有至少八个不同符号的符号流。 最后,调制器可以被配置成调制符号流。

    Unequal error protection Reed-Muller code generator and decoder
    9.
    发明授权
    Unequal error protection Reed-Muller code generator and decoder 有权
    不等错误保护Reed-Muller代码生成器和解码器

    公开(公告)号:US06854082B1

    公开(公告)日:2005-02-08

    申请号:US09994556

    申请日:2001-11-27

    Applicant: Dojun Rhee

    Inventor: Dojun Rhee

    CPC classification number: H03M13/35 H03M13/356

    Abstract: An unequal error protection Reed-Muller code and method for designing a generator matrix and decoder. A conventional RM code is concatenated with the combination of itself and a subcode of itself. The new generator matrix is decomposed to include empty submatrices. The resulting generator matrix allows parallel decoding of separate portions of the received code word vectors.

    Abstract translation: 用于设计发生器矩阵和解码器的不等错误保护Reed-Muller代码和方法。 常规的RM代码与其本身和自身的子代码的组合连接。 新的生成矩阵被分解为包括空子矩阵。 所得到的生成矩阵允许对接收到的码字向量的分离部分进行并行解码。

    Trellis code modulation decoder structure for advanced digital television receiver
    10.
    发明授权
    Trellis code modulation decoder structure for advanced digital television receiver 失效
    网格码调制解码器结构,适用于高级数字电视接收机

    公开(公告)号:US06201563B1

    公开(公告)日:2001-03-13

    申请号:US09093362

    申请日:1998-06-08

    Applicant: Dojun Rhee

    Inventor: Dojun Rhee

    Abstract: An ATV receiver is provided with a 16-state trellis decoder to achieve improved performance in the presence of NTSC co-channel interference. In one embodiment, the ATV receiver comprises a tuner, a comb filter, and a trellis decoder. The tuner is configured to downmix a selected channel frequency signal to an intermediate frequency signal, where the comb filter is configurable to screen out most of the NTSC co-channel interference. The intermediate frequency receive signal is modified by the comb filter to resemble a partial response signal. The trellis decoder the demodulates the partial response signal in an improved fashion taking into account the state of the trellis encoder and the partial response channel. The trellis decoder may have a 16 state trellis comprised of four 4-state butterflies wherein each edge in the trellis is a single transition.

    Abstract translation: ATV接收机设有16状态网格解码器,以在存在NTSC同频道干扰的情况下实现改进的性能。 在一个实施例中,ATV接收机包括调谐器,梳状滤波器和网格解码器。 调谐器被配置为将所选择的频道信号下混合到中频信号,其中梳状滤波器可配置为屏蔽大部分NTSC同频道干扰。 中频接收信号由梳状滤波器修改为类似于部分响应信号。 网格解码器以考虑到网格编码器和部分响应信道的状态的改进方式解调部分响应信号。 网格解码器可以具有由四个4状态蝴蝶组成的16状态网格,其中网格中的每个边缘是单个转换。

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