发明授权
- 专利标题: Semiconductor device and method of manufacturing the same
- 专利标题(中): 半导体装置及其制造方法
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申请号: US701913申请日: 1996-08-23
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公开(公告)号: US5817551A公开(公告)日: 1998-10-06
- 发明人: Taizo Fujii , Takehiro Hirai , Sugao Fujinaga
- 申请人: Taizo Fujii , Takehiro Hirai , Sugao Fujinaga
- 申请人地址: JPX Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JPX Osaka
- 优先权: JPX7-217227 19950825; JPX7-231189 19950908
- 主分类号: H01L21/265
- IPC分类号: H01L21/265 ; H01L21/336 ; H01L21/8234 ; H01L27/06 ; H01L27/092 ; H01L29/10 ; H01L29/78
摘要:
In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented. Consequently, there is provided a semiconductor device having a DMOSFET mounted thereon which has a reduced on-resistance and suppresses the activation of a parasitic bipolar transistor due to reduced variations in threshold voltage and a high-quality gate oxide film.
公开/授权文献
- US5246755A Sealing material for electric wire connection 公开/授权日:1993-09-21