公开(公告)号：US5415698A

公开(公告)日：1995-05-16

申请号：US84421

申请日：1993-06-29

申请人： Sugao Fujinaga ,  Naomi Arita ,  Yoshitaka Dansui

发明人： Sugao Fujinaga ,  Naomi Arita ,  Yoshitaka Dansui

IPC分类号： H01L21/00 ,  H01L21/306 ,  B08B3/04

CPC分类号： H01L21/02052 ,  H01L21/67057

摘要： A method for cleaning a substrate of the present invention, in which a plurality of substrates are placed substantially parallel with each other are dipped into a cleaning solution to remove particles adhering to each of the substrates, includes the step of dipping the substrates into the cleaning solution at a speed (V) through a surface of the cleaning solution, wherein the speed (V) for dipping the substrates into the cleaning solution, a minimum distance (l) among distances between the substrates, a length (L) of the substrates measured in a dip direction thereof, and a speed (v) at which the particles are transferred along the surface of the cleaning solution in a vertical direction with respect to back faces of the substrates satisfy the expression: lV.gtoreq.vL.

摘要翻译： 将多个基板彼此平行放置的本发明的基板的清洗方法浸渍在清洗液中，除去附着在各基板上的颗粒，包括将基板浸渍到清洗中的步骤 溶液以一定速度（V）通过清洁溶液的表面，其中用于将基底浸入清洁溶液中的速度（V）在基底之间的距离之间的最小距离（l），基底的长度（L） 在其浸渍方向上测量，并且颗粒沿着相对于基板的背面在垂直方向上的清洁溶液的表面转移的速度（v）满足以下表达式：lV> / = vL。

公开(公告)号：US06927594B2

公开(公告)日：2005-08-09

申请号：US10869872

申请日：2004-06-18

申请人： Sugao Fujinaga ,  Nobuyuki Moriwaki

发明人： Sugao Fujinaga ,  Nobuyuki Moriwaki

IPC分类号： H01L21/66 ,  G11C29/02 ,  H01L21/3205 ,  H01L23/52 ,  G01R31/26

CPC分类号： G11C29/025 ,  G11C29/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： An evaluation device for evaluating a semiconductor device, used for evaluating electric characteristics of an electrical connection member provided in a vertical direction to a substrate surface, includes a unit circuit having a switching transistor in which a gate thereof connected to a signal line and one of a source and a drain thereof is connected to a first interconnect, and a first resistance element in which one terminal is connected to the other one of the source and the drain of the switching transistor and the other terminal is connected to a second interconnect. The first resistance element constituting each unit circuit includes at least one electrical connection member.

摘要翻译： 用于评估用于评估在垂直方向上设置在基板表面上的电连接部件的电特性的半导体装置的评估装置包括具有开关晶体管的单元电路，其中连接到信号线的栅极和 其源极和漏极连接到第一互连，并且第一电阻元件，其中一个端子连接到开关晶体管的源极和漏极中的另一个，而另一个端子连接到第二互连。 构成每个单元电路的第一电阻元件包括至少一个电连接构件。

公开(公告)号：US5905284A

公开(公告)日：1999-05-18

申请号：US859366

申请日：1997-05-20

申请人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

发明人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/1095

摘要： In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented. Consequently, there is provided a semiconductor device having a DMOSFET mounted thereon which has a reduced on-resistance and suppresses the activation of a parasitic bipolar transistor due to reduced variations in threshold voltage and a high-quality gate oxide film.

摘要翻译： 在DMOSFET的N-漏极扩散层的源极侧的部分中形成P-体扩散层时，以大的倾斜角注入P型杂质离子，以到达N +栅电极下方的一部分区域 通过使用具有对应于要形成DMOSFET的体漫射层的区域的开口和N +栅电极被激活的抗蚀剂膜。 此后，分别在P-体扩散层和N-漏极扩散层中形成N +源极扩散层和N +漏极扩散层。 由于不需要进行高温驱入工艺来将P型杂质离子引入到N +栅电极下面的区域，所以由杂质引起的阈值电压和栅极氧化膜的劣化的降低或变化 可以防止从N +栅电极扩散。 因此，提供了一种其上安装有DMOSFET的半导体器件，其具有降低的导通电阻，并且由于阈值电压的变化和高质量的栅氧化膜而抑制了寄生双极晶体管的激活。

公开(公告)号：US5817551A

公开(公告)日：1998-10-06

申请号：US701913

申请日：1996-08-23

申请人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

发明人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/66674 ,  H01L29/7801 ,  H01L29/1095

摘要： In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented. Consequently, there is provided a semiconductor device having a DMOSFET mounted thereon which has a reduced on-resistance and suppresses the activation of a parasitic bipolar transistor due to reduced variations in threshold voltage and a high-quality gate oxide film.

摘要翻译： 在DMOSFET的N-漏极扩散层的源极侧的部分中形成P-体扩散层时，以大的倾斜角注入P型杂质离子，以到达N +栅电极下方的一部分区域 通过使用具有对应于要形成DMOSFET的体漫射层的区域的开口和N +栅电极被激活的抗蚀剂膜。 此后，分别在P-体扩散层和N-漏极扩散层中形成N +源极扩散层和N +漏极扩散层。 由于不需要进行高温驱入工艺来将P型杂质离子引入到N +栅电极下面的区域，所以由杂质引起的阈值电压和栅极氧化膜的劣化的降低或变化 可以防止从N +栅电极扩散。 因此，提供了一种其上安装有DMOSFET的半导体器件，其具有降低的导通电阻，并且由于阈值电压的变化和高质量的栅氧化膜而抑制了寄生双极晶体管的激活。

公开(公告)号：US5851863A

公开(公告)日：1998-12-22

申请号：US629248

申请日：1996-04-08

申请人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

发明人： Taizo Fujii ,  Takehiro Hirai ,  Sugao Fujinaga

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/8238

CPC分类号： H01L21/8249 ,  H01L27/0623

摘要： An n-type buried layer and an n-type epitaxial layer that becomes a collector layer of a pnp transistor are formed on a semiconductor substrate. A well and the collector layer are formed. Ions of an n-type impurity are implanted through a photoresist mask, to form an intrinsic base layer of the pnp transistor and a PT-VT diffusion layer with punchthrough stopper and threshold control functions of a pMOSFET. Ions of a p-type impurity are implanted through a photoresist mask at a shallow implantation depth than the previous step, to form an intrinsic base layer of an npn transistor and a channel dope layer of the pMOSFET. A buried channel is formed under the gate of the pMOSFET. Therefore pMOSFETs with good characteristics can be obtained. In this way, the present invention achieves bipolar transistors and MOSFETs with good characteristics, without having to increase the number of fabrication steps and the number of photoresist masks.

摘要翻译： 在半导体衬底上形成成为pnp晶体管的集电极层的n型掩埋层和n型外延层。 形成阱和集电极层。 通过光致抗蚀剂掩模注入n型杂质的离子，以形成pnp晶体管的本征基极层和具有穿通阻挡层的PT-VT扩散层和pMOSFET的阈值控制功能。 p型杂质的离子通过光致抗蚀剂掩模以比上一步骤浅的注入深度注入，以形成pMOSFET的npn晶体管和沟道掺杂层的本征基极层。 在pMOSFET的栅极下方形成掩埋沟道。 因此，可以获得具有良好特性的pMOSFET。 以这种方式，本发明实现了具有良好特性的双极晶体管和MOSFET，而不必增加制造步骤的数量和光致抗蚀剂掩模的数量。