发明授权
US5817572A Method for forming multileves interconnections for semiconductor
fabrication
失效
用于形成用于半导体制造的多层互连的方法
- 专利标题: Method for forming multileves interconnections for semiconductor fabrication
- 专利标题(中): 用于形成用于半导体制造的多层互连的方法
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申请号: US768790申请日: 1996-12-18
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公开(公告)号: US5817572A公开(公告)日: 1998-10-06
- 发明人: Chien Chiang , David B. Fraser
- 申请人: Chien Chiang , David B. Fraser
- 申请人地址: CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L21/44
摘要:
A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.
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