公开(公告)号：US06303464B1

公开(公告)日：2001-10-16

申请号：US08774382

申请日：1996-12-30

申请人： Eng T. Gaw ,  Quat T. Vu ,  David B. Fraser ,  Chien Chiang ,  Ian A. Young ,  Thomas N. D. Marieb

发明人： Eng T. Gaw ,  Quat T. Vu ,  David B. Fraser ,  Chien Chiang ,  Ian A. Young ,  Thomas N. D. Marieb

IPC分类号： H01L2176

CPC分类号： H01L21/7682

摘要： A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.

摘要翻译： 降低电容互连系统。 第一金属层形成在形成在半导体衬底上的第一介电层上方的预定水平。 第一金属层级形成多个互连线，其中每个互连线通过包括具有最高纵横比的沟槽的沟槽与每个相邻的互连线分开。 在第一金属层和互连线之间的沟槽中形成第二电介质层，使得具有空隙尖端的封闭空隙与金属层的顶部基本一致地形成在至少每个沟槽中，其纵横比高于 预定的最小纵横比，其中具有最高纵横比的沟槽中的封闭空隙具有至少占沟槽体积的15％的空隙体积。

公开(公告)号：US5886410A

公开(公告)日：1999-03-23

申请号：US670624

申请日：1996-06-26

申请人： Chien Chiang ,  Chuanbin Pan ,  Vicky M. Ochoa ,  Sychyi Fang ,  David B. Fraser ,  Joyce C. Sum ,  Gary William Ray ,  Jeremy A. Theil

发明人： Chien Chiang ,  Chuanbin Pan ,  Vicky M. Ochoa ,  Sychyi Fang ,  David B. Fraser ,  Joyce C. Sum ,  Gary William Ray ,  Jeremy A. Theil

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5222 ,  H01L2924/0002

摘要： An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

摘要翻译： 提供互连系统。 互连系统包括硅衬底和形成在硅衬底上的第一介电层。 互连系统还包括形成在第一介电层上的至少两个导电线的第一级。 所述互连系统还包括形成在所述至少两个导电线之间的低介电常数材料区域。 互连系统还包括形成在聚合物区域上的第一硬掩模。

公开(公告)号：US5817572A

公开(公告)日：1998-10-06

申请号：US768790

申请日：1996-12-18

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/76829 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S438/945 ,  Y10S438/975

摘要： A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

摘要翻译： 描述了用于形成用于半导体制造和半导体器件的互连的方法具有这样的互连。 第一图案化电介质层形成在半导体衬底之上并且具有填充有导电材料的第一开口。 在第一电介质层上形成另一图案化电介质层，并且在至少一部分导电材料上具有第二开口。 第一图案化电介质层可以在图案化其它图案化的介电层时用作蚀刻停止。 此外，在形成另一个图案化的介电层之前，可以在第一图案化电介质层上方和导电材料之上形成电介质蚀刻停止层。 该电介质蚀刻停止层可以在图案化其它图案化的介电层时用作蚀刻停止。 第二开口露出电介质蚀刻停止层的一部分。 去除电介质蚀刻停止层的暴露部分。 第二个开口填充有导电材料。

公开(公告)号：US5739579A

公开(公告)日：1998-04-14

申请号：US707027

申请日：1996-09-10

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/76829 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S438/945 ,  Y10S438/975

摘要： A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filed with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

摘要翻译： 描述了用于形成用于半导体制造和半导体器件的互连的方法具有这样的互连。 第一图案化电介质层形成在半导体衬底之上并且具有带导电材料的第一开口。 在第一电介质层上形成另一图案化电介质层，并且在至少一部分导电材料上具有第二开口。 第一图案化电介质层可以在图案化其它图案化的介电层时用作蚀刻停止。 此外，在形成另一个图案化的介电层之前，可以在第一图案化电介质层上方和导电材料之上形成电介质蚀刻停止层。 该电介质蚀刻停止层可以在图案化其它图案化的介电层时用作蚀刻停止。 第二开口露出电介质蚀刻停止层的一部分。 去除电介质蚀刻停止层的暴露部分。 第二个开口填充有导电材料。

公开(公告)号：US6040628A

公开(公告)日：2000-03-21

申请号：US769549

申请日：1996-12-19

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/58

CPC分类号： H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002

摘要： A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer. Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.

摘要翻译： 描述了一种制造半导体集成电路的结构和方法。 第一图案化导电层在图案的沟槽内包含低介电常数的第一绝缘材料，例如有机聚合物。 在第一图案化导电层上形成第二绝缘材料，例如具有比第一绝缘材料更大的机械强度和导热性以及更高介电常数的二氧化硅或其它绝缘材料。 填充有导电插塞的第二绝缘材料内的通孔和第二图案化的导电层可以形成在第二绝缘材料上。 该结构可以根据需要重复多次以形成完整的集成电路。

公开(公告)号：US06949831B2

公开(公告)日：2005-09-27

申请号：US10890716

申请日：2004-07-13

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58

CPC分类号： H01L23/5222 ,  H01L21/76837 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for microelectronic devices indudes a plurality of patterned, spaced apart, substantially co-planar, conductive lines, a first portion of the plurality of conductive lines having a first Intralayer dielectric of a first dielectric constant therebetween, and a second portion of the plurality of conductive lines having a second intralayer dielectric of a second dielectric constant therebetween. By providing in-plane selectability of dielectric constant, in-plane decoupling capacitance, as between power supply nodes, can be increased, while in-plane parasitic capacitance between signal lines can be reduced.

摘要翻译： 用于微电子器件的互连结构包括多个图案化的间隔开的基本共平面的导电线，多个导线的第一部分具有第一介电常数介于第一介电常数之间，第二部分是 多个导电线具有第二介电常数介于其间的第二介电常数。 通过提供介电常数的面内可选择性，可以增加在电源节点之间的平面内去耦电容，而可以减小信号线之间的面内寄生电容。

公开(公告)号：US06239019B1

公开(公告)日：2001-05-29

申请号：US09291401

申请日：1999-04-13

申请人： Chien Chiang ,  David B. Fraser

发明人： Chien Chiang ,  David B. Fraser

IPC分类号： H01L214763

CPC分类号： H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of fabrication of a semiconductor integrated circuit is described. A first patterned electrically conductive layer contains a low dielectric constant first insulating material such as organic polymer within the trenches of the pattern. A second insulating material such as a silicon dioxide or other insulating material having a greater. mechanical strength and thermal conductivity and a higher dielectric constant than the first insulating material is formed over the first patterned electrically conductive layer Vias within the second insulating material filled with electrically conductive plugs and a second patterned electrically conductive layer may be formed on the second insulating material. The structure can be repeated as many times as needed to form a completed integrated circuit.

摘要翻译： 描述了一种制造半导体集成电路的结构和方法。 第一图案化导电层在图案的沟槽内包含低介电常数的第一绝缘材料，例如有机聚合物。 第二绝缘材料，例如二氧化硅或其它具有较大的绝缘材料的绝缘材料。 在填充有导电插塞的第二绝缘材料内的第一图案化导电层通孔之上形成机械强度和热导率以及比第一绝缘材料更高的介电常数，并且可以在第二绝缘材料上形成第二图案化导电层 。 该结构可以根据需要重复多次以形成完整的集成电路。

公开(公告)号：US6037249A

公开(公告)日：2000-03-14

申请号：US2124

申请日：1997-12-31

申请人： Chien Chiang ,  David B. Fraser ,  Vicky Ochoa ,  Chuanbin Pan ,  Sing-Mo H. Tzeng

发明人： Chien Chiang ,  David B. Fraser ,  Vicky Ochoa ,  Chuanbin Pan ,  Sing-Mo H. Tzeng

IPC分类号： H01L21/764 ,  H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/764

摘要： A process for forming air gaps in an interconnect system is disclosed. At least two conductive lines are formed upon a substrate. A low-dielectric constant material (LDCM) is formed between the at least two conductive lines. Formation of the LDCM creates first and second adhesive forces between the LDCM and the at least two conductive lines and between the LDCM and the substrate, respectively. The LDCM is expanded. A dielectric layer is formed onto the LDCM and the at least two conductive lines. Formation of the dielectric layer creates a third adhesive force between the LDCM and the dielectric layer. The LDCM is contracted. Contraction of the LDCM resulting from a fourth force within the LDCM. Each of the first, second, and third adhesive forces are substantially stronger than the fourth force.

摘要翻译： 公开了一种在互连系统中形成气隙的工艺。 在基板上形成至少两条导线。 在至少两条导线之间形成低介电常数材料（LDCM）。 LDCM的形成分别在LDCM和至少两个导电线之间以及LDCM和衬底之间分别产生第一和第二粘合力。 LDCM扩大。 在LDCM和至少两根导电线上形成介电层。 电介质层的形成在LDCM和电介质层之间产生第三粘附力。 LDCM签约。 由LDCM内的第四个力导致的LDCM收缩。 第一，第二和第三粘合力中的每一个基本上比第四力强。

公开(公告)号：US6027995A

公开(公告)日：2000-02-22

申请号：US135618

申请日：1998-08-18

申请人： Chien Chiang ,  Chuanbin Pan ,  Vicky M. Ochoa ,  Sychyi Fang ,  David B. Fraser ,  Joyce C. Sum ,  Gary William Ray ,  Jeremy A. Theil

发明人： Chien Chiang ,  Chuanbin Pan ,  Vicky M. Ochoa ,  Sychyi Fang ,  David B. Fraser ,  Joyce C. Sum ,  Gary William Ray ,  Jeremy A. Theil

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5222 ,  H01L2924/0002

摘要： An interconnect system is provided. The interconnect system includes a silicon substrate and a first dielectric layer formed upon the silicon substrate. The interconnect system also includes a first level of at least two electrically conductive lines formed upon the first dielectric layer. The interconnect system further includes a region of low dielectric constant material formed between the at least two electrically conductive lines. The interconnect system also includes a first hard mask formed upon the polymer region.

摘要翻译： 提供互连系统。 互连系统包括硅衬底和形成在硅衬底上的第一介电层。 互连系统还包括形成在第一介电层上的至少两个导电线的第一级。 所述互连系统还包括形成在所述至少两个导电线之间的低介电常数材料区域。 互连系统还包括形成在聚合物区域上的第一硬掩模。

公开(公告)号：US5880030A

公开(公告)日：1999-03-09

申请号：US978105

申请日：1997-11-25

申请人： Sychyi Fang ,  Chien Chiang ,  David B. Fraser

发明人： Sychyi Fang ,  Chien Chiang ,  David B. Fraser

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L2924/0002 ,  Y10S438/978

摘要： A high density, low capacitance, interconnect structure for microelectronic devices has unlanded vias formed with organic polymer intralayer dielectric material having substantially vertical sidewalls. A method of producing unlanded vias includes forming a planarized organic polymer intra-layer dielectric between conductors, forming an inorganic dielectric over the conductor and organic polymer layer, patterning a photoresist layer such that openings in the photoresist layer overlap portions of both the conductor and the intra-layer dielectric, etching the inorganic dielectric and then concurrently stripping the photoresist and anisotropically etching the organic polymer intra-layer dielectric. A second conductor is typically deposited into the via opening so as to form an electrical connection to the first conductor. A silicon based insulator containing an organic polymer can alternatively be used to form the intra-layer dielectric.

摘要翻译： 用于微电子器件的高密度，低电容互连结构具有形成有具有基本上垂直侧壁的有机聚合物内层介电材料的无空洞通孔。 一种制造无衬底通孔的方法包括在导体之间形成平面化的有机聚合物层内电介质，在导体和有机聚合物层上形成无机电介质，图案化光致抗蚀剂层，使得光致抗蚀剂层中的开口与导体和 层内电介质，蚀刻无机电介质，然后同时剥离光致抗蚀剂并各向异性蚀刻有机聚合物层内电介质。 通常将第二导体沉积到通孔开口中，以形成与第一导体的电连接。 也可以使用包含有机聚合物的硅基绝缘体来形成层间电介质。