发明授权
- 专利标题: Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
- 专利标题(中): 减少可编程逻辑器件中硅处理缺陷影响的手段和装置
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申请号: US742770申请日: 1996-11-01
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公开(公告)号: US5825197A公开(公告)日: 1998-10-20
- 发明人: Christopher F. Lane , Srinivas T. Reddy , Bonnie I-Keh Wang
- 申请人: Christopher F. Lane , Srinivas T. Reddy , Bonnie I-Keh Wang
- 申请人地址: CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: CA San Jose
- 主分类号: G06F11/20
- IPC分类号: G06F11/20 ; G06F15/78 ; H03K19/177 ; H03K19/003 ; H03K19/173
摘要:
A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
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