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1.发明授权Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices 失效减少可编程逻辑器件中硅处理缺陷影响的手段和装置
公开(公告)号：US5825197A
公开(公告)日：1998-10-20
申请号：US742770
申请日：1996-11-01
IPC分类号： G06F11/20 , G06F15/78 , H03K19/177 , H03K19/003 , H03K19/173
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
摘要翻译： 可编程逻辑阵列集成电路具有几个可编程逻辑电路的常规列和备用列，该备用列包括包含在常规列中的可编程逻辑电路的子集。 在备用列中复制的常规列中的电路中存在缺陷的情况下，由此复制的常规列逻辑功能从列移动到列，使得备用列电路被使用，并且缺陷规则 不使用列电路。 在备用列中未重复的常规列函数不会移动。 用于编程列的数据有选择地路由到具有或不具有列移位的列，这取决于该数据是用于在备用列中是否被复制的功能。
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2.发明授权Programmable logic array integrated circuits with improved interconnection conductor utilization 失效具有改进的互连导体利用率的可编程逻辑阵列集成电路
公开(公告)号：US5694058A
公开(公告)日：1997-12-02
申请号：US619072
申请日：1996-03-20
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17796
摘要： In order to increase routing flexibility for the output signals of logic modules in programmable logic array integrated circuit devices, the output signal of each logic module can be swapped with the output signal of another logic module by a first level of signal swapping circuitry. The output signals of the first level of swapping circuitry can be further swapped with output signals of other first level swapping circuits by a second level of signal swapping circuitry to provide still more routing flexibility for the logic module output signals.
摘要翻译： 为了增加可编程逻辑阵列集成电路器件中的逻辑模块的输出信号的布线灵活性，每个逻辑模块的输出信号可以通过第一级信号交换电路与另一个逻辑模块的输出信号进行交换。 第一级交换电路的输出信号可以通过第二级信号交换电路进一步与其它第一级交换电路的输出信号交换，以为逻辑模块输出信号提供更多的路由灵活性。
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