发明授权
US5893135A Flash memory array with two interfaces for responding to RAS and CAS
signals
失效
具有两个接口的闪存阵列，用于响应RAS和CAS信号
- 专利标题： Flash memory array with two interfaces for responding to RAS and CAS signals
- 专利标题（中）： 具有两个接口的闪存阵列，用于响应RAS和CAS信号
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申请号： US587799申请日： 1995-12-27
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公开(公告)号： US5893135A公开(公告)日： 1999-04-06
- 发明人: Robert N. Hasbun , Andrew H. Gafken
- 申请人： Robert N. Hasbun , Andrew H. Gafken
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： G11C7/10
- IPC分类号： G11C7/10 ; G11C16/26 ; G06F12/00 ; G06F13/00
摘要：
An arrangement for accessing a non-volatile memory array including providing a signal having a first condition if an access is a read and a second condition if an access is for any other operation; reading data directly from an address in the non-volatile memory array if the signal is a first condition; and performing any other access of the non-volatile memory array utilizing a command-centric interface if the signal is a second condition.
公开/授权文献
- US4649268A Imaging dynodes arrangement 公开/授权日：1987-03-10
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