公开(公告)号：US20080104705A1

公开(公告)日：2008-05-01

申请号：US11554330

申请日：2006-10-30

申请人： Robert N. Hasbun

发明人： Robert N. Hasbun

IPC分类号： H04L9/32

CPC分类号： H04L63/104 ,  G06F21/105 ,  G06F21/604 ,  G06F2221/2101 ,  G06F2221/2129 ,  G06F2221/2135 ,  G06F2221/2137 ,  G06F2221/2141 ,  G06F2221/2151

摘要： A system is disclosed for centralized management of access permissions to specific devices on client terminals using a group policy framework. The system identifies a unique device identifier for a specific device, and allows policy to be set for the specific device based on identifying the specific device by its unique device identifier.

摘要翻译： 公开了一种用于使用组策略框架来集中管理对客户终端上的特定设备的访问权限的系统。 系统识别特定设备的唯一设备标识符，并且允许通过其唯一的设备标识符来识别特定设备来为特定设备设置策略。

公开(公告)号：US07062623B2

公开(公告)日：2006-06-13

申请号：US10672593

申请日：2003-09-26

申请人： James R. Vogt ,  Robert N. Hasbun ,  John P. Brizek

发明人： James R. Vogt ,  Robert N. Hasbun ,  John P. Brizek

IPC分类号： G06F13/00

CPC分类号： G06F12/1466 ,  G06F2212/2022

摘要： A method and device for providing hidden storage in non-volatile memory. A memory device is disclosed comprising a main flash array. A hidden storage area is connected to the main flash array. The hidden storage area can not be accessed without a valid password according to the present memory device.

摘要翻译： 一种在非易失性存储器中提供隐藏存储的方法和装置。 公开了一种包括主闪存阵列的存储器件。 隐藏的存储区域连接到主闪存阵列。 根据本存储器设备，如果没有有效的密码，则无法访问隐藏的存储区域。

公开(公告)号：US06834323B2

公开(公告)日：2004-12-21

申请号：US09748825

申请日：2000-12-26

申请人： Lance W. Dover ,  Robert N. Hasbun ,  Paul D. Ruby ,  William T. Reaves

发明人： Lance W. Dover ,  Robert N. Hasbun ,  Paul D. Ruby ,  William T. Reaves

IPC分类号： G06F1200

CPC分类号： G11C29/48 ,  G11C16/3454 ,  G11C29/46

摘要： A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. A host processor verifies external to the memory the programming of the plurality of data words into the memory. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.

摘要翻译： 一种其中输入存储器的特殊编程模式的方法。 特殊编程模式禁用内存的内部验证。 存储器包括用于程序验证的自动化电路。 多个字被编程到存储器中，而没有存储器执行内部程序验证。 主机处理器将存储器外部的多个数据字的编程验证到存储器中。 退出特殊编程模式，启用内存的内部程序验证。 还描述了一种具有主机处理器和具有特殊编程模式电路的存储器的装置。

公开(公告)号：US06449735B1

公开(公告)日：2002-09-10

申请号：US08672983

申请日：1996-07-01

申请人： David A. Edwards ,  Robert N. Hasbun

发明人： David A. Edwards ,  Robert N. Hasbun

IPC分类号： H02H305

CPC分类号： G06F11/22

摘要： A memory module including a flash EEPROM memory array designed to be joined to a memory bus of a computer, BIOS processes including system status test processes stored in the array, diagnostic processes stored in the array to provide data indicating malfunctions in the computer, accessing processes stored in the array for calling the system status test processes and the diagnostic processes even though the computer fails to boot, and communication processes stored in the array for transferring results produced by the system status test processes and the diagnostic processes for use in servicing the computer.

摘要翻译： 一种存储器模块，包括被设计为连接到计算机的存储器总线的闪存EEPROM存储器阵列，包括存储在阵列中的系统状态测试过程的BIOS处理，存储在阵列中的诊断过程以提供指示计算机中的故障的数据，访问进程 存储在阵列中用于调用系统状态测试进程和诊断过程，即使计算机无法启动，以及存储在阵列中的通信过程用于传送由系统状态测试过程产生的结果和用于维护计算机的诊断过程 。

公开(公告)号：US06412040B2

公开(公告)日：2002-06-25

申请号：US09489182

申请日：2000-01-20

申请人： Robert N. Hasbun ,  David A. Edwards

发明人： Robert N. Hasbun ,  David A. Edwards

IPC分类号： G06F1730

CPC分类号： G06F12/0246 ,  G06F8/654 ,  G06F9/5016 ,  H04M1/24 ,  H04Q11/045 ,  H04Q2213/13034 ,  H04Q2213/13096 ,  H04Q2213/13097 ,  H04Q2213/1316 ,  H04Q2213/13202 ,  H04Q2213/13209 ,  H04Q2213/13217 ,  H04Q2213/13302 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  Y10S707/99953 ,  Y10S707/99957

摘要： Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. In one embodiment, a method of reliably re-allocating a first object stored within a block erasable nonvolatile memory includes the step of allocating space for a second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of re-allocating a first object stored within a block erasable nonvolatile memory includes the step of invalidating the first object, if the first object has an unreliable type of recovery level. Space is allocated for the second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of reliably re-allocating a first object stored within the block erasable nonvolatile memory includes the step of allocating space for the second object. A write of the second object is initiated and the writing of the second object is tracked. The first object is invalidated after completion of writing the second object, if the first object has a reliable type of recovery. In one embodiment, the first object resides within a first portion of nonvolatile memory and the instructions for performing the described methods reside in a second portion of nonvolatile memory. The first and second portions can reside within a same nonvolatile memory such as a symmetrically blocked flash electrically erasable programmable read only memory.

摘要翻译： 描述在具有分叉存储架构的非易失性存储器内分配，写入，读取，分配，重新分配和回收空间的方法。 在一个实施例中，可靠地重新分配存储在块可擦除非易失性存储器中的第一对象的方法包括为第二对象分配空间的步骤。 启动第二个对象的写入，并跟踪第二个对象的写入。 在另一个实施例中，重新分配存储在块可擦除非易失性存储器中的第一对象的方法包括如果第一对象具有不可靠类型的恢复级别，则使第一对象无效的步骤。 为第二个对象分配空间。 启动第二个对象的写入，并跟踪第二个对象的写入。 在另一个实施例中，可靠地重新分配存储在块可擦除非易失性存储器内的第一对象的方法包括为第二对象分配空间的步骤。 启动第二个对象的写入，并跟踪第二个对象的写入。 如果第一个对象具有可靠的恢复类型，则第一个对象在完成写入第二个对象后无效。 在一个实施例中，第一对象位于非易失性存储器的第一部分内，并且用于执行所述方法的指令驻留在非易失性存储器的第二部分中。 第一和第二部分可以驻留在相同的非易失性存储器中，例如对称阻挡的闪存电可擦除可编程只读存储器。

公开(公告)号：US5867721A

公开(公告)日：1999-02-02

申请号：US978998

申请日：1997-11-28

申请人： Mark P. Leinwander ,  Steven E. Wells ,  Robert N. Hasbun

发明人： Mark P. Leinwander ,  Steven E. Wells ,  Robert N. Hasbun

IPC分类号： G06F12/06 ,  G06F12/08

CPC分类号： G06F12/06

摘要： A circuit for selecting a select line from a plurality of first and second select lines is described. Each of an array of integrated circuit (IC) packages is coupled to (1) one of the first select lines and (2) at least one of the second select lines. The circuit includes a decoder for decoding a select data to select the select line, and circuitry for modifying the select data before the select data is applied to the decoder when each of the second select lines is not coupled to an IC device within each of the IC packages to ensure that the select line is not one of the second select lines. When each of the first and second select lines is coupled to an IC device within each of the IC packages, the circuitry for modifying does not modify the select data. A method for selecting a selected IC device within a selected IC package of an array of IC packages is also described.

摘要翻译： 描述用于从多个第一和第二选择线选择选择线的电路。 集成电路（IC）封装的阵列中的每一个耦合到（1）第一选择线之一和（2）至少一个第二选择线。 该电路包括用于对选择数据进行解码以选择选择线的解码器，以及用于当每个第二选择线未耦合到每个第一选择线内的IC器件时，在选择数据被施加到解码器之前修改选择数据的电路 IC封装，以确保选择线不是第二选择线之一。 当第一和第二选择线中的每一个耦合到每个IC封装内的IC器件时，用于修改的电路不修改选择数据。 还描述了用于在IC封装阵列的选定IC封装内选择所选IC器​​件的方法。

公开(公告)号：US5822256A

公开(公告)日：1998-10-13

申请号：US811194

申请日：1997-03-05

申请人： Mark E. Bauer ,  Steven Wells ,  David M. Brown ,  Johnny Javanifard ,  Sherif Sweha ,  Robert N. Hasbun ,  Gary J. Gallagher ,  Mamun Rashid ,  Rodney R. Rozman ,  Glen Hawk ,  George Blanchard ,  Mark Winston ,  Richard D. Pashley

发明人： Mark E. Bauer ,  Steven Wells ,  David M. Brown ,  Johnny Javanifard ,  Sherif Sweha ,  Robert N. Hasbun ,  Gary J. Gallagher ,  Mamun Rashid ,  Rodney R. Rozman ,  Glen Hawk ,  George Blanchard ,  Mark Winston ,  Richard D. Pashley

IPC分类号： G11C11/56 ,  G11C29/00 ,  G11C29/44 ,  G11C7/00

CPC分类号： G11C29/88 ,  G11C11/5621 ,  G11C11/5628 ,  G11C29/44 ,  G11C2211/5641

摘要： A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

摘要翻译： 描述了允许使用部分功能的集成电路存储器的方法和电路。 存储器阵列被分离成单独的块，每个块可以被隔离以最小化由缺陷使得不可用的存储器阵列的量。 还提供电路以将阵列内的存储器单元编程为至少三个电荷量之一，从而增加剩余功能块提供的存储量。

公开(公告)号：US5815434A

公开(公告)日：1998-09-29

申请号：US537132

申请日：1995-09-29

申请人： Robert N. Hasbun ,  Frank P. Janecek

发明人： Robert N. Hasbun ,  Frank P. Janecek

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C11/34

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C17/146 ,  G11C2211/5641

摘要： A method for performing multiple writes before an erase to a nonvolatile memory cell is described. A first bit is stored at a first level of a nonvolatile memory cell. A second bit is stored at a second level of the nonvolatile memory cell. A method of erasing a nonvolatile memory cell is described. A level indicator that indicates the next level of the nonvolatile memory cell to write to is incremented. A method of reading a nonvolatile memory cell includes recalling a level indicator. The nonvolatile memory cell is then sensed at a level indicated by the level indicator to determine the state of the memory cell.

摘要翻译： 描述了在擦除非易失性存储单元之前执行多次写入的方法。 第一位存储在非易失性存储单元的第一级。 第二位存储在非易失性存储单元的第二级。 描述擦除非易失性存储单元的方法。 指示写入的非易失性存储单元的下一个电平的电平指示器递增。 读取非易失性存储单元的方法包括调用电平指示符。 然后在由电平指示器指示的电平处感测非易失性存储器单元，以确定存储器单元的状态。

公开(公告)号：US5671388A

公开(公告)日：1997-09-23

申请号：US433614

申请日：1995-05-03

申请人： Robert N. Hasbun

发明人： Robert N. Hasbun

IPC分类号： G06F12/02 ,  G11C11/56

CPC分类号： G11C11/56 ,  G06F12/0246 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C16/16 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C29/00

摘要： A memory contains a plurality of memory cells that are capable of storing one or more bits of data in each memory cell. The memory stores, in response to a write operation, data corresponding to the write operation in a first set of the memory cells such that each cell of the first set of the memory cells stores a single bit. Thereafter, data from the first set of memory cells are transferred to a second set of the memory cells such that each cell of the second set of the memory cells stores more than a single bit of data. The write operation to the first set of cells is executed in a foreground operation, and in a subsequent background operation, data from the first set of memory cells are transferred to the second set of memory cells. The memory cells are non-volatile flash electrically erasable programmable read only memory (EEPROM) cells, and therefore require erasure before programming. Typically, memory cells are reclaimed in a background operation. However, if not enough memory cells are available for a write operation, then a set of memory cells are reclaimed in a foreground operation, and more than one bit of the data are stored in the reclaimed memory cells.

摘要翻译： 存储器包含能够在每个存储单元中存储一个或多个数据位的多个存储器单元。 存储器响应于写入操作存储与第一组存储器单元中的写入操作相对应的数据，使得第一组存储器单元的每个单元存储单个位。 此后，来自第一组存储器单元的数据被传送到存储器单元的第二组，使得第二组存储器单元的每个单元存储多于一位数据。 在前台操作中执行对第一组单元的写入操作，并且在随后的后台操作中，来自第一组存储器单元的数据被传送到第二组存储器单元。 存储单元是非易失性闪存电可擦除可编程只读存储器（EEPROM）单元，因此在编程之前需要擦除。 通常，在后台操作中回收存储单元。 然而，如果没有足够的存储器单元可用于写入操作，则在前台操作中回收一组存储器单元，并且多于一个位的数据存储在再生存储单元中。

公开(公告)号：US5586285A

公开(公告)日：1996-12-17

申请号：US20063

申请日：1993-02-19

申请人： Robert N. Hasbun ,  Steven Wells

发明人： Robert N. Hasbun ,  Steven Wells

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F13/10

CPC分类号： G06F3/0601 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2212/401 ,  Y02B60/1225

摘要： A solid state memory disk with increased reserve memory is described. The solid state memory disk includes an array of solid state memory devices for storing user data and reserve memory, which includes both free memory and dirty memory. The solid state memory disk also includes a controller, a clean-up state machine, and a data compressor. The data compressor increases reserve memory by compressing data received from a host and coupling compressed data to the array of memory devices under the control of the controller. In response to write commands from the host, the controller writes a first sector data, which has been compressed, to a first location in a first block within a memory device. Reserve memory within the array is thus increased, so long as the maximum number of sectors the host is allowed to write is less the average compression ratio of the data compressor multiplied by the capacity of the solid state disk. A method of increasing reserve memory in a solid state disk is also described.

摘要翻译： 描述了具有增加的备用存储器的固态存储盘。 固态存储盘包括用于存储用户数据和预留存储器的固态存储器件阵列，其包括空闲存储器和脏存储器。 固态存储盘还包括控制器，清理状态机和数据压缩器。 数据压缩器通过压缩从主机接收的数据来增加预留存储器，并将压缩数据耦合到控制器控制下的存储器件阵列。 响应于来自主机的写命令，控制器将已压缩的第一扇区数据写入存储器设备内的第一块中的第一位置。 因此，只要主机允许写入扇区的最大数量少于数据压缩器的平均压缩比乘以固态磁盘的容量，阵列中的保留内存就会增加。 还描述了在固态盘中增加储备存储器的方法。