发明授权
US5909126A Programmable logic array integrated circuit devices with interleaved
logic array blocks
失效
具有交错逻辑阵列块的可编程逻辑阵列集成电路器件
- 专利标题: Programmable logic array integrated circuit devices with interleaved logic array blocks
- 专利标题(中): 具有交错逻辑阵列块的可编程逻辑阵列集成电路器件
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申请号: US672676申请日: 1996-06-28
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公开(公告)号: US5909126A公开(公告)日: 1999-06-01
- 发明人: Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
- 申请人: Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
- 申请人地址: CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: CA San Jose
- 主分类号: H03K19/04
- IPC分类号: H03K19/04 ; H03K19/177
摘要:
A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.
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