发明授权
US5914616A FPGA repeatable interconnect structure with hierarchical interconnect
lines
失效
具有分层互连线路的FPGA可重复互连结构
- 专利标题： FPGA repeatable interconnect structure with hierarchical interconnect lines
- 专利标题（中）： 具有分层互连线路的FPGA可重复互连结构
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申请号： US806997申请日： 1997-02-26
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公开(公告)号： US5914616A公开(公告)日： 1999-06-22
- 发明人: Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
- 申请人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
- 申请人地址： CA San Jose
- 专利权人： XILINX, Inc.
- 当前专利权人： XILINX, Inc.
- 当前专利权人地址： CA San Jose
- 主分类号： H01L25/00
- IPC分类号： H01L25/00 ; H03K19/173 ; H03K19/177
摘要：
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.
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