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    Latch based optimization during implementation of circuit designs for programmable logic devices
    2.
    发明授权
    Latch based optimization during implementation of circuit designs for programmable logic devices 有权
    实现可编程逻辑器件电路设计时的基于锁存器的优化

    公开(公告)号：US08146041B1

    公开(公告)日：2012-03-27

    申请号：US13180782

    申请日：2011-07-12

    申请人： Sankaranarayanan Srinivasan ,  Sridhar Krishnamurthy ,  Brian D. Philofsky ,  Kamal Chaudhary ,  Anirban Rahut

    发明人： Sankaranarayanan Srinivasan ,  Sridhar Krishnamurthy ,  Brian D. Philofsky ,  Kamal Chaudhary ,  Anirban Rahut

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made by a computer as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

    摘要翻译： 实现可编程逻辑器件内的电路设计的计算机实现的方法可以包括选择电路设计的至少一个电路元件。 所选择的电路元件可以被转换成锁存器。 在将所选择的电路元件转换为锁存器之后，可以在电路设计上执行时序分析。 当电路设计的时序改善时，计算机可以确定电路设计的时序是否改善，并且可以接受所选择的电路元件到锁存器的转换。 可以输出电路设计。

    Placing partitioned circuit designs within iterative implementation flows
    3.
    发明授权
    Placing partitioned circuit designs within iterative implementation flows 有权
    将分隔电路设计放在迭代实现流程中

    公开(公告)号：US07590960B1

    公开(公告)日：2009-09-15

    申请号：US11787925

    申请日：2007-04-18

    申请人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

    发明人： Raymond Kong ,  Navaratnasothie Selvakkumaran ,  Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5072

    摘要： A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

    摘要翻译： 将分割电路设计的电路元件放置在目标可编程逻辑器件（PLD）上的方法可以包括将电路设计的电路元件映射到电路设计的相应分区，选择电路设计的电路元件，以及选择候选 位于目标PLD的逻辑边界内。 该方法还可以包括至少部分地根据所选择的电路元件是否属于与已经放置在逻辑边界内的至少一个其它电路元件的电路设计的相同分区来验证所选择的电路元件的候选位置。 所选择的电路元件可以根据验证选择性地放置在候选位置。

    Congestion estimation for programmable logic devices
    4.
    发明授权
    Congestion estimation for programmable logic devices 失效
    可编程逻辑器件的拥塞估计

    公开(公告)号：US07146590B1

    公开(公告)日：2006-12-05

    申请号：US10927734

    申请日：2004-08-27

    申请人： Kamal Chaudhary

    发明人： Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method of estimating congestion for a programmable logic device can include calculating a number of fan-in paths for each resource in the programmable logic device and calculating a number of fan-out paths for each resource in the programmable logic device. For each resource of the programmable logic device, a number of paths having different path characteristics can be determined and a probability can be assigned thereto. One or more measures of congestion can be computed according to the determining step.

    摘要翻译： 估计可编程逻辑器件的拥塞的方法可以包括为可编程逻辑器件中的每个资源计算多个扇入路径，并为可编程逻辑器件中的每个资源计算多个扇出路径。 对于可编程逻辑器件的每个资源，可以确定具有不同路径特性的多个路径，并且可以分配概率。 可以根据确定步骤计算拥塞的一个或多个措施。

    Method for analytical placement of cells using density surface representations
    5.
    发明授权
    Method for analytical placement of cells using density surface representations 有权
    使用密度表面表示法分析细胞的方法

    公开(公告)号：US06415425B1

    公开(公告)日：2002-07-02

    申请号：US09262727

    申请日：1999-03-04

    申请人： Kamal Chaudhary ,  Sudip K. Nag

    发明人： Kamal Chaudhary ,  Sudip K. Nag

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： A method for analytical placement of cells using density surface representations. The placement of the cells is characterized as density surface fun which is two-dimensional and continuous. The cells are iteratively moved from areas having higher densities of placed cells to areas having lower densities of placed cells using the density surface function.

    摘要翻译： 使用密度表面表示法分析细胞的方法。 细胞的放置被表征为二维和连续的密度表面乐趣。 使用密度表面函数将细胞从具有较高密度的放置细胞的区域迭代地移动到具有较低密度的置换细胞的区域。

    Enhanced incremental placement during physical synthesis
    9.
    发明授权
    Enhanced incremental placement during physical synthesis 有权
    在物理合成期间增强增量放置

    公开(公告)号：US07428718B1

    公开(公告)日：2008-09-23

    申请号：US11361369

    申请日：2006-02-24

    申请人： Amit Singh ,  Kamal Chaudhary

    发明人： Amit Singh ,  Kamal Chaudhary

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5054

    摘要： A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the critical region can be assigned to sites located on, or proximate to, the line according to connectivity.

    摘要翻译： 放置目标设备的电路设计的方法可以包括识别具有至少一个输入块和至少一个输出块的关键区域，并确定从输入块开始并延伸到输出块的线。 可以根据连接性将关键区域的块分配给位于或接近线路的站点。

    Interconnect structure for a programmable logic device
    10.
    发明授权
    Interconnect structure for a programmable logic device 有权

    公开(公告)号：US06448808B2

    公开(公告)日：2002-09-10

    申请号：US09929977

    申请日：2001-08-15

    申请人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    发明人： Steven P. Young ,  Kamal Chaudhary ,  Trevor J. Bauer

    IPC分类号： H01L2500

    CPC分类号： H03K19/1737 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17796

    摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.