发明授权
US5917668A Synchronous read channel employing a frequency synthesizer for locking a
timing recovery phase-lock loop to a reference frequency
失效
采用频率合成器的同步读通道,用于将定时恢复锁相环锁定到参考频率
- 专利标题: Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency
- 专利标题(中): 采用频率合成器的同步读通道,用于将定时恢复锁相环锁定到参考频率
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申请号: US822174申请日: 1997-03-21
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公开(公告)号: US5917668A公开(公告)日: 1999-06-29
- 发明人: Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
- 申请人: Richard T. Behrens , Trent Dudley , Neal Glover , David R. Welland
- 申请人地址: CA Fremont
- 专利权人: Cirrus Logic, Inc.
- 当前专利权人: Cirrus Logic, Inc.
- 当前专利权人地址: CA Fremont
- 主分类号: G11B5/012
- IPC分类号: G11B5/012 ; G11B5/09 ; G11B20/10 ; G11B20/12 ; G11B20/14 ; G11B20/18 ; G11B27/30 ; H03M13/31
摘要:
A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.
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