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    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency
    1.
    发明授权
    Synchronous read channel employing a frequency synthesizer for locking a timing recovery phase-lock loop to a reference frequency 失效
    采用频率合成器的同步读通道，用于将定时恢复锁相环锁定到参考频率

    公开(公告)号：US5917668A

    公开(公告)日：1999-06-29

    申请号：US822174

    申请日：1997-03-21

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

    CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

    摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To ensure a small frequency error when timing recovery acquisition mode is entered, the timing recovery phase-lock loop (PLL) is first locked to a nominal read frequency which is the same as the write frequency. This is accomplished by multiplexing the output of the write frequency synthesizer into the timing recovery PLL in a lock-to-reference mode. Thereafter, the analog signal from the read head is multiplexed into the timing recovery PLL in order to acquire the actual frequency and phase of an acquisition preamble recorded prior to the user data.

    摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 为了在进入定时恢复采集模式时确保小的频率误差，定时恢复锁相环（PLL）首先被锁定到与写入频率相同的标称读取频率。 这是通过将写入频率合成器的输出以锁定参考模式复用到定时恢复PLL来实现的。 此后，来自读取头的模拟信号被多路复用到定时恢复PLL中，以便获取在用户数据之前记录的获取前导码的实际频率和相位。

    Timing recovery circuit for synchronous waveform sampling
    2.
    发明授权
    Timing recovery circuit for synchronous waveform sampling 失效
    同步波形采样定时恢复电路

    公开(公告)号：US5359631A

    公开(公告)日：1994-10-25

    申请号：US954350

    申请日：1992-09-30

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover ,  David R. Welland

    IPC分类号： G11B20/10 ,  G11B20/14 ,  H03D13/00 ,  H03L7/00 ,  H03L7/085 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10 ,  H03D3/24

    CPC分类号： G11B20/10037 ,  G11B20/1403 ,  H03D13/005 ,  H03L7/091 ,  H04L7/0334 ,  H04L7/04 ,  H04L7/046 ,  H04L7/10

    摘要： A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

    摘要翻译： 具有模拟数字转换器以对模拟信号进行采样的定时电路，用于控制模数转换器的采样时间的受控振荡器，用于检测模拟信号中的脉冲的电路，相位误差电路，以从 另一个创建相位误差测量和频率误差电路，将两个样本相加在一起以创建频率误差测量。 两个样本取自脉冲的任一侧。 相位误差测量由受控振荡器用于调整采样定时以在脉冲的所需位置采样。 电路还包含用于补偿不对称脉冲的常数值，并补偿靠近检测到的脉冲发生的其他脉冲。 电路还插入已知频率代替模拟信号以建立受控振荡器的频率。

    Sampled amplitude read channel employing a discrete time noise generator for calibration
    9.
    发明授权
    Sampled amplitude read channel employing a discrete time noise generator for calibration 失效
    采用离散时间噪声发生器进行校准的采样幅度读取通道

    公开(公告)号：US5786951A

    公开(公告)日：1998-07-28

    申请号：US658763

    申请日：1996-06-05

    申请人： David R. Welland ,  Richard T. Behrens ,  Iuri Mehr

    发明人： David R. Welland ,  Richard T. Behrens ,  Iuri Mehr

    IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B5/035

    CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10037 ,  G11B5/09

    摘要： This invention provides apparatus and a method to assist in calibrating a read channel in a magnetic data storage system. More particularly, the invention provides a read channel including a digital noise generator. During a calibration procedure, the digital noise generator injects an analog noise signal into the read channel, thereby increasing the read channel's bit-error rate, and consequently allowing rapid calibration of the read channel. The digital noise generator comprises a number of linear feedback shift registers that together generate a pseudo-random digital word sequence, and a digital-to-analog converter that converts the pseudo-random digital word sequence into the analog noise signal. The digital-to-analog converter comprises a plurality of one-bit digital-to-analog converters whose outputs are summed by an analog adder. This configuration causes the analog noise signal to exhibit a binomial probability distribution which is close to a normal probability distribution for a sufficiently large number of linear feedback shift registers. The linear feedback shift registers are driven by a clock that operates at a higher frequency than the rate at which data is processed in the read channel. The analog noise signal, therefore, has bandwidth that is wider than that of the data, thereby insuring that calibration of the read channel includes effects due to aliasing. The digital noise generator is disabled while the read head passes over synchronization marks and embedded servo wedges.

    摘要翻译： 本发明提供了一种辅助校准磁数据存储系统中的读通道的装置和方法。 更具体地，本发明提供了一种包括数字噪声发生器的读通道。 在校准过程中，数字噪声发生器将模拟噪声信号注入读通道，从而增加读通道的误码率，从而允许读通道的快速校准。 数字噪声发生器包括一起产生伪随机数字字序列的多个线性反馈移位寄存器，以及将伪随机数字字序列转换为模拟噪声信号的数 - 模转换器。 数模转换器包括多个1位数模转换器，其输出由模拟加法器相加。 该配置使得模拟噪声信号呈现二进制概率分布，其接近足够大数量的线性反馈移位寄存器的正态概率分布。 线性反馈移位寄存器由在读通道中处理数据的频率更高的时钟运行的时钟驱动。 因此，模拟噪声信号具有比数据宽的带宽，从而确保读通道的校准包括由于混叠引起的影响。 读取头通过同步标记和嵌入式伺服楔时，数字噪声发生器被禁用。