One terminals of capacitors are connected to multiple input terminals via first switch means which can select a positive or negative logic of an input signal, and the other terminals of the capacitors are commonly connected (point b) to first differential input of a differential input/output type sense amplifier via second switch. The commonly connected portion of the capacitors are connected to second differential input of the differential input/output type sense amplifier, the second differential input having a polarity opposite to that of the first differential input, thereby suppressing an increase in circuit scale due to an increase in the number of bits, and assuring high-speed arithmetic operations.