A semiconductor test system is capable of performing a simultaneous test for testing a plurality of memory devices at the same time as well as carrying out re-write operations in a page by page manner of the memory address, to reduce an overall test time. The semiconductor test system includes a hold means 5 which detects fail information in the output signal from a pass/fail judgement circuit 1, within a page of the memory address, and holds the fail information. A judgement means 11 is provided to determine, at the end of each page, whether the failure has occurred in each of the memory devices under test. A re-write control circuit 100 is provided for transmitting an output signal of the flip-flop 11 as a re-write prohibition signal 102. A plurality of re-write control circuits 200, 300 may be additionally provided corresponding to the number of devices to be tested.