发明授权
US5929667A Method and apparatus for protecting circuits subjected to high voltage
失效
用于保护经受高压的电路的方法和装置
- 专利标题: Method and apparatus for protecting circuits subjected to high voltage
- 专利标题(中): 用于保护经受高压的电路的方法和装置
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申请号: US872374申请日: 1997-06-10
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公开(公告)号: US5929667A公开(公告)日: 1999-07-27
- 发明人: Wagdi W. Abadeer , George Maria Braceras , John Connor , Donald Albert Evans
- 申请人: Wagdi W. Abadeer , George Maria Braceras , John Connor , Donald Albert Evans
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: H03K19/003
- IPC分类号: H03K19/003 ; H03K3/00
摘要:
A CMOS off-chip driver circuit and a method of operating the circuit are provided. The circuit has two pull-down transistors and two pull-up transistors, each pull-up transistor has a gate. A voltage source provides voltage at a logic-high output voltage of approximately 3.3 volts. An output terminal is provided. Initially, a logic-low output voltage is applied to the gate of each of the two pull-up transistors. A condition is detected in which the voltage of the output terminal is greater than a predetermined threshold voltage. The predetermined threshold voltage is between approximately 2.5 volts and approximately 3.3 volts. The voltage applied to the gate of each of the pull-up transistors is raised to an intermediate level that is greater than the logic-low output voltage and less than the logic-high output voltage while the condition is detected. The intermediate level may be approximately 1.5 volts. A clamping mechanism is provided for sinking current from the output terminal to the voltage source, when the voltage of the output terminal is greater than the logic-high output voltage. The clamping mechanism sources current to the output terminal from a ground conductor that provides the logic-low output voltage to the pull-down transistor, when the voltage of the output terminal is less than the logic-low output voltage.
公开/授权文献
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