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    Method and apparatus for protecting circuits subjected to high voltage
    1.
    发明授权
    Method and apparatus for protecting circuits subjected to high voltage 失效
    用于保护经受高压的电路的方法和装置

    公开(公告)号：US5929667A

    公开(公告)日：1999-07-27

    申请号：US872374

    申请日：1997-06-10

    申请人： Wagdi W. Abadeer ,  George Maria Braceras ,  John Connor ,  Donald Albert Evans

    发明人： Wagdi W. Abadeer ,  George Maria Braceras ,  John Connor ,  Donald Albert Evans

    IPC分类号： H03K19/003 ,  H03K3/00

    CPC分类号： H03K19/00315

    摘要： A CMOS off-chip driver circuit and a method of operating the circuit are provided. The circuit has two pull-down transistors and two pull-up transistors, each pull-up transistor has a gate. A voltage source provides voltage at a logic-high output voltage of approximately 3.3 volts. An output terminal is provided. Initially, a logic-low output voltage is applied to the gate of each of the two pull-up transistors. A condition is detected in which the voltage of the output terminal is greater than a predetermined threshold voltage. The predetermined threshold voltage is between approximately 2.5 volts and approximately 3.3 volts. The voltage applied to the gate of each of the pull-up transistors is raised to an intermediate level that is greater than the logic-low output voltage and less than the logic-high output voltage while the condition is detected. The intermediate level may be approximately 1.5 volts. A clamping mechanism is provided for sinking current from the output terminal to the voltage source, when the voltage of the output terminal is greater than the logic-high output voltage. The clamping mechanism sources current to the output terminal from a ground conductor that provides the logic-low output voltage to the pull-down transistor, when the voltage of the output terminal is less than the logic-low output voltage.

    摘要翻译： 提供CMOS片外驱动电路和操作电路的方法。 该电路具有两个下拉晶体管和两个上拉晶体管，每个上拉晶体管都有一个栅极。 电压源以大约3.3伏特的逻辑高输出电压提供电压。 提供输出端子。 最初，将两个上拉晶体管中的每一个的栅极施加逻辑低输出电压。 检测出输出端子的电压大于预定阈值电压的条件。 预定的阈值电压在大约2.5伏和大约3.3伏之间。 在检测到条件时，施加到每个上拉晶体管的栅极的电压升高到大于逻辑低输出电压并小于逻辑高输出电压的中间电平。 中间电平可以是大约1.5伏特。 当输出端子的电压大于逻辑高输出电压时，提供钳位机构用于将电流从输出端子吸收到电压源。 当输出端子的电压小于逻辑低输出电压时，钳位机构将电流从提供逻辑低输出电压的接地导体输出到下拉晶体管。

    Receiver input voltage protection circuit
    2.
    发明授权
    Receiver input voltage protection circuit 失效
    接收器输入电压保护电路

    公开(公告)号：US5815354A

    公开(公告)日：1998-09-29

    申请号：US821497

    申请日：1997-03-21

    申请人： George Maria Braceras ,  John Connor ,  Donald Albert Evans

    发明人： George Maria Braceras ,  John Connor ,  Donald Albert Evans

    IPC分类号： H02H9/04 ,  H02H9/00

    CPC分类号： H02H9/046

    摘要： An off-chip receiver circuit for interfacing an integrated circuit of a 2.5 Volt CMOS technology to a 3.3 Volt LVTTL bus. The off-chip receiver includes protection circuitry for preventing overstressing of the gate oxide caused by undershoot/overshoot peaks of -1 volt to 6 volts on the input.

    摘要翻译： 用于将2.5伏CMOS技术的集成电路与3.3伏的LVTTL总线接口的片外接收器电路。 片外接收器包括用于防止由输入端上的-1伏至6伏特的下冲/过冲峰值引起的栅极氧化物的过应力的保护电路。

    ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY
    4.
    发明申请
    ADJUSTING BIT-LINE DISCHARGE TIME IN MEMORY ARRAYS BASED ON CHARACTERIZED WORD-LINE DELAY AND GATE DELAY 失效
    基于特征字长延迟和门延时调整存储器阵列中的位线放电时间

    公开(公告)号：US20140071775A1

    公开(公告)日：2014-03-13

    申请号：US13606342

    申请日：2012-09-07

    申请人： Donald Albert Evans ,  Rasoju Veerabadra Chary ,  Richard John Stephani ,  Bijan Kumar Ghosh ,  Ronald Brian Steele

    发明人： Donald Albert Evans ,  Rasoju Veerabadra Chary ,  Richard John Stephani ,  Bijan Kumar Ghosh ,  Ronald Brian Steele

    IPC分类号： G11C7/22

    CPC分类号： G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/222 ,  G11C7/227 ,  G11C29/02 ,  G11C29/023 ,  G11C2029/1204

    摘要： A memory tracking circuit controls discharge duration of a tracking bit-line based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. The tracking circuit (i) extends the discharge duration when one or more of (a) the propagation delay and (b) the transistor-based gate delay is shorter than an uncontrolled discharge duration of the tracking bit-line, and (ii) does not extend the discharge duration otherwise. Based on the discharge duration, the tracking circuit activates a reset signal that resets a clock-pulse generator to switch the memory from an access operation to a recess state. Controlling the discharge duration, and consequently the reset signal, based on the propagation delay and the gate delay allows the clock-pulse generator to adjust access times to account for the memory array configuration and process, temperature, and voltage conditions.

    摘要翻译： 存储器跟踪电路基于（i）在传播延迟之后在跟踪行的远端接收的信号和（ii）施加到基于晶体管的门延迟的信号来控制跟踪位线的放电持续时间。 跟踪电路（i）在（a）传播延迟和（b）基于晶体管的栅极延迟短于跟踪位线的不受控制的放电持续时间的一个或多个时延长放电持续时间，并且（ii） 否则不延长放电持续时间。 基于放电持续时间，跟踪电路激活复位信号，其复位时钟脉冲发生器以将存储器从访问操作切换到凹陷状态。 基于传播延迟和门延迟来控制放电持续时间以及因此复位信号允许时钟脉冲发生器调整存取时间以解决存储器阵列配置和处理，温度和电压条件。

    Memory device with phase distribution circuit for controlling relative durations of precharge and active phases
    7.
    发明授权
    Memory device with phase distribution circuit for controlling relative durations of precharge and active phases 有权
    具有相位分配电路的存储器件，用于控制预充电和有源相的相对持续时间

    公开(公告)号：US08284622B2

    公开(公告)日：2012-10-09

    申请号：US12893153

    申请日：2010-09-29

    申请人： Donald Albert Evans ,  Richard J. McPartland ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Donald Albert Evans ,  Richard J. McPartland ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227

    摘要： A memory device comprises a memory array and a phase distribution circuit coupled to the memory array. In one aspect, the phase distribution circuit is operative to control respective durations of a precharge phase and an active phase of a memory cycle of the memory array based on relative transistor characteristics of a tracked precharge transistor of a first conductivity type and a tracked memory cell transistor of a second conductivity type different than the first conductivity type. For example, the phase distribution circuit may comprise a first tracking transistor of the first conductivity type for tracking the precharge transistor of the first conductivity type and a second tracking transistor of the second conductivity type for tracking the memory cell transistor of the second conductivity type. The relative transistor characteristics may comprise relative strengths of the tracked precharge and memory cell transistors.

    摘要翻译： 存储器件包括耦合到存储器阵列的存储器阵列和相位分配电路。 一方面，相位分配电路可操作以基于第一导电类型的跟踪预充电晶体管和跟踪的存储单元的相对晶体管特性来控制存储器阵列的存储周期的预充电阶段和有效相位的相应持续时间 不同于第一导电类型的第二导电类型的晶体管。 例如，相位分配电路可以包括用于跟踪第一导电类型的预充电晶体管的第一导电类型的第一跟踪晶体管和用于跟踪第二导电类型的存储单元晶体管的第二导电类型的第二跟踪晶体管。 相对晶体管特性可以包括跟踪的预充电和存储单元晶体管的相对强度。

    Reduced leakage driver circuit and memory device employing same
    8.
    发明授权
    Reduced leakage driver circuit and memory device employing same 有权
    减少泄漏驱动电路和采用其的存储器件

    公开(公告)号：US07633830B2

    公开(公告)日：2009-12-15

    申请号：US11947210

    申请日：2007-11-29

    申请人： Donald Albert Evans ,  Richard J. McPartland ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Donald Albert Evans ,  Richard J. McPartland ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08

    摘要： A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

    摘要翻译： 一种用于存储器阵列的行线驱动电路，包括多个存储器单元和耦合到存储器单元的多个行线，用于选择性地访问存储器单元包括适于连接到对应的一行行的输出级和连接到控制电路的控制电路 到输出阶段。 输出级在给定存储器周期的有效相位期间操作，以将对应的行线驱动为作为由驱动器电路接收的至少一个地址信号的函数的电位。 控制电路至少在存储器周期的非活动阶段期间产生至少一个禁止输出级的控制信号，从而基本上消除了驱动器电路中的漏电流路径。

    Memory device with error correction based on automatic logic inversion
    9.
    发明授权
    Memory device with error correction based on automatic logic inversion 失效
    基于自动逻辑反相的误差校正存储器件

    公开(公告)号：US08365044B2

    公开(公告)日：2013-01-29

    申请号：US11738827

    申请日：2007-04-23

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C29/00

    CPC分类号： G11C29/846 ,  G11C17/14

    摘要： A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

    摘要翻译： 存储器件包括耦合到存储器阵列的存储器阵列和纠错电路。 错误校正电路被配置为在从存储器阵列检索的数据字中识别与存储器阵列中的预定缺陷位置相对应的至少一个位位置，并且通过自动反转在该存储器阵列中的逻辑值来产生校正数据字 识别位位置。 这种自动逻辑反转方法特别适用于校正与高密度ROM器件中的通孔缺陷和弱位缺陷相关联的输出数据错误。

    Accelerated searching for content-addressable memory
    10.
    发明授权
    Accelerated searching for content-addressable memory 有权
    加速搜索内容可寻址内存

    公开(公告)号：US07391633B2

    公开(公告)日：2008-06-24

    申请号：US11460045

    申请日：2006-07-26

    申请人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    发明人： Dennis E. Dudeck ,  Donald Albert Evans ,  Hai Quang Pham ,  Wayne E. Werner ,  Ronald James Wozniak

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C7/067

    摘要： A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.

    摘要翻译： 与包括多个匹配线的CAM电路一起使用的感测电路和连接到匹配线的多个CAM单元包括至少一个电荷共享电路和连接到电荷共享电路的至少一个开关电路。 开关电路用于根据提供给开关电路的第一控制信号选择性地将电荷共享电路连接到匹配线中的对应的一个。 感测电路还包括连接到对应匹配线的至少一个比较器电路，用于产生指示提供给连接到相应匹配线的至少一个给定的一个CAM单元的搜索数据和存储的数据之间的匹配的输出信号 在给定的CAM单元格中。 电荷共享电路用于去除相应匹配线上的电荷量，以便结合CAM单元的搜索操作来减小相应匹配线上的电压。