公开(公告)号：US5929667A

公开(公告)日：1999-07-27

申请号：US872374

申请日：1997-06-10

申请人： Wagdi W. Abadeer ,  George Maria Braceras ,  John Connor ,  Donald Albert Evans

发明人： Wagdi W. Abadeer ,  George Maria Braceras ,  John Connor ,  Donald Albert Evans

IPC分类号： H03K19/003 ,  H03K3/00

CPC分类号： H03K19/00315

摘要： A CMOS off-chip driver circuit and a method of operating the circuit are provided. The circuit has two pull-down transistors and two pull-up transistors, each pull-up transistor has a gate. A voltage source provides voltage at a logic-high output voltage of approximately 3.3 volts. An output terminal is provided. Initially, a logic-low output voltage is applied to the gate of each of the two pull-up transistors. A condition is detected in which the voltage of the output terminal is greater than a predetermined threshold voltage. The predetermined threshold voltage is between approximately 2.5 volts and approximately 3.3 volts. The voltage applied to the gate of each of the pull-up transistors is raised to an intermediate level that is greater than the logic-low output voltage and less than the logic-high output voltage while the condition is detected. The intermediate level may be approximately 1.5 volts. A clamping mechanism is provided for sinking current from the output terminal to the voltage source, when the voltage of the output terminal is greater than the logic-high output voltage. The clamping mechanism sources current to the output terminal from a ground conductor that provides the logic-low output voltage to the pull-down transistor, when the voltage of the output terminal is less than the logic-low output voltage.

摘要翻译： 提供CMOS片外驱动电路和操作电路的方法。 该电路具有两个下拉晶体管和两个上拉晶体管，每个上拉晶体管都有一个栅极。 电压源以大约3.3伏特的逻辑高输出电压提供电压。 提供输出端子。 最初，将两个上拉晶体管中的每一个的栅极施加逻辑低输出电压。 检测出输出端子的电压大于预定阈值电压的条件。 预定的阈值电压在大约2.5伏和大约3.3伏之间。 在检测到条件时，施加到每个上拉晶体管的栅极的电压升高到大于逻辑低输出电压并小于逻辑高输出电压的中间电平。 中间电平可以是大约1.5伏特。 当输出端子的电压大于逻辑高输出电压时，提供钳位机构用于将电流从输出端子吸收到电压源。 当输出端子的电压小于逻辑低输出电压时，钳位机构将电流从提供逻辑低输出电压的接地导体输出到下拉晶体管。

公开(公告)号：US06278339B1

公开(公告)日：2001-08-21

申请号：US09735679

申请日：2000-12-13

申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

IPC分类号： H03H738

摘要： An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

公开(公告)号：US06249193B1

公开(公告)日：2001-06-19

申请号：US09320902

申请日：1999-05-27

申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

IPC分类号： H03H738

CPC分类号： H04L25/0278

摘要： An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

摘要翻译： 阻抗匹配系统和用于高频输入 - 输出设备的驱动电路输出端的阻抗匹配网络。 阻抗匹配网络包括可调节长度的传输线，其长度与驱动器电路输出上的瞬变的大小成比例地调整，并且输入阻抗是纯反应的，并且是其长度的函数。 可调长度传输线的目的是通过为驱动器电路的接收器电路的阻抗的无功分量提供匹配阻抗来降低瞬态电压。 在优选实施例中，阻抗匹配网络包括形成在系统卡上的两条平行导线，由可移动短截线短路，并且与驱动电路并联连接。 可选地，阻抗匹配网络还包括控制电路，其检测驱动器电路输出端的过冲和下冲，并提供与过冲和下冲的大小成比例的控制电流到电磁调节机构，该电磁调节机构对可移动短截线进行线性调节，与 控制电流。

公开(公告)号：US6140885A

公开(公告)日：2000-10-31

申请号：US255997

申请日：1999-02-23

申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

IPC分类号： H04L25/02 ,  H03H7/38 ,  H03H7/40

CPC分类号： H04L25/0278

摘要： An impedance matching system and a network for automatic impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises a control circuit which varies a control voltage proportionally to the frequency of voltage transients that occur on the driver circuit output, an adjustment mechanism which provides a linear motion proportional to the control voltage, and an adjustable length transmission line whose length is adjusted in proportion to the frequency of voltage transients on the driver circuit output and whose impedance, which is purely reactive, is proportional to its length. The purpose of the adjustable length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver network to the driver circuit. In the preferred embodiment, the impedance matching network is manufactured on the same chip as the driver circuit.

摘要翻译： 阻抗匹配系统和用于高频输入输出设备的驱动电路输出端的自动阻抗匹配网络。 阻抗匹配网络包括控制电路，该控制电路根据驱动器电路输出上发生的电压瞬变的频率成比例地改变控制电压，提供与控制电压成比例的线性运动的调节机构，以及可调长度传输线，其长度 与驱动器电路输出上的电压瞬变的频率成比例地调整，并且其纯粹无功的阻抗与其长度成比例。 可调长度传输线的目的是通过为接收机网络的阻抗的无功分量提供与驱动器电路的匹配阻抗来减小瞬态电压。 在优选实施例中，阻抗匹配网络在与驱动器电路相同的芯片上制造。

公开(公告)号：US20120280356A1

公开(公告)日：2012-11-08

申请号：US13552695

申请日：2012-07-19

申请人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William Tonti

发明人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William Tonti

IPC分类号： H01L29/06

CPC分类号： H01L21/76232

摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.

摘要翻译： 本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。 在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。 退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。 距离对于每个沟槽和每个相邻的隔离区域是成比例的。

公开(公告)号：US20120128033A1

公开(公告)日：2012-05-24

申请号：US12950508

申请日：2010-11-19

申请人： Wagdi W. Abadeer ,  Cathryn J. Christiansen ,  John A. Fifield ,  Dimitris P. Ioannou ,  Tom C. Lee ,  Lilian Kamal

发明人： Wagdi W. Abadeer ,  Cathryn J. Christiansen ,  John A. Fifield ,  Dimitris P. Ioannou ,  Tom C. Lee ,  Lilian Kamal

IPC分类号： G01K7/16

CPC分类号： G01K7/16

摘要： A system and a method for measuring temperature within an operating circuit use a Wheatstone bridge within a temperature sensing circuit. One of the resistors in the Wheatstone bridge is a thermally sensitive resistive material layer within the operating circuit. The other three resistors are thermally isolated from the operating circuit. Particular configurations of NFET and PFET devices are used to provide enhanced measurement sensitivity within the temperature sensing circuit that includes the Wheatstone bridge.

摘要翻译： 用于测量操作电路内的温度的系统和方法使用温度感测电路内的惠斯通电桥。 惠斯通电桥中的一个电阻器是操作电路内的热敏电阻材料层。 其他三个电阻器与工作电路热绝缘。 NFET和PFET器件的特殊配置用于在包括惠斯通电桥的温度检测电路中提供增强的测量灵敏度。

公开(公告)号：US07873921B2

公开(公告)日：2011-01-18

申请号：US11948308

申请日：2007-11-30

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

IPC分类号： G06F17/50 ,  H03L7/00

CPC分类号： G06F17/5063 ,  G06F2217/78

摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

摘要翻译： 一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

公开(公告)号：US07825469B2

公开(公告)日：2010-11-02

申请号：US11850488

申请日：2007-09-05

申请人： Wagdi W. Abadeer ,  John A. Fifield

发明人： Wagdi W. Abadeer ,  John A. Fifield

IPC分类号： H01L29/72

CPC分类号： H04N5/374 ,  H04N5/365 ,  H04N5/3651 ,  H04N5/378

摘要： The present disclosure is directed to a CMOS active pixel sensor that compensates for variations in a threshold voltage of a source follower contained therein. A structure in accordance with an embodiment includes: a replica source follower transistor; a system for creating a current in said replica source follower transistor such that a gate-source voltage of said replica source follower is substantially equal to a threshold voltage of said replica source follower; and a current mirror for biasing the isolation source follower transistor at a same current density as the replica source follower transistor.

摘要翻译： 本公开涉及一种CMOS有源像素传感器，其补偿其中包含的源极跟随器的阈值电压的变化。 根据实施例的结构包括：复制源极跟随器晶体管; 用于在所述复制源跟随器晶体管中产生电流的系统，使得所述复制源极跟随器的栅极 - 源极电压基本上等于所述复制源极跟随器的阈值电压; 以及电流镜，用于以与复制源极跟随器晶体管相同的电流密度偏置隔离源跟随器晶体管。

公开(公告)号：US07814449B2

公开(公告)日：2010-10-12

申请号：US11873515

申请日：2007-10-17

申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Joseph A. Iadanza

发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Joseph A. Iadanza

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

摘要翻译： 公开了具有多个源极区域的可变延迟场效应晶体管（FET）的设计结构的实施例，其可被单独地和选择性地偏置以提供到单个漏极区域的电连接。 延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。 这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。 相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。 相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

公开(公告)号：US07763531B2

公开(公告)日：2010-07-27

申请号：US11846544

申请日：2007-08-29

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthler, Jr. ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthler, Jr. ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L21/425

CPC分类号： B07C5/344 ,  G01R31/2831

摘要： The disclosure describes an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FETs.

摘要翻译： 本公开描述了在同一衬底上具有多个半导体鳍片的集成电路，其具有不同的宽度和可变间隔。 形成电路的方法包括使用不同类型的心轴的侧壁图像转印过程。 翅片厚度和翅片翅片间距由用于在心轴上形成氧化物侧壁的氧化工艺控制，更具体地，通过处理时间和使用固有的，氧化增强的和/或氧化抑制的心轴来控制。 翅片厚度也通过使用与氧化物侧壁结合或代替氧化物侧壁的侧壁间隔来控制。 具体地，单独的氧化物侧壁的图像，侧壁间隔物的图像和/或侧壁间隔物和氧化物侧壁的组合图像被转移到半导体层中以形成散热片。 可以使用具有不同厚度和可变间隔的散热片来形成单个多鳍FET。