发明授权
US5941971A Bus bridge transaction checker for correct resolution of combined data
cycles
失效
总线桥交易检查器,用于正确解决组合数据周期
- 专利标题: Bus bridge transaction checker for correct resolution of combined data cycles
- 专利标题(中): 总线桥交易检查器,用于正确解决组合数据周期
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申请号: US904195申请日: 1997-07-31
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公开(公告)号: US5941971A公开(公告)日: 1999-08-24
- 发明人: Hamilton B. Carter
- 申请人: Hamilton B. Carter
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: G06F11/267
- IPC分类号: G06F11/267 ; G06F13/38 ; G06F13/42
摘要:
A method to correctly resolve combined data cycles in a bus bridge's posted write buffer is described. In a computer system with a bus bridge connecting a plurality of system buses, a state machine model is created for each bus in the system. A bus cycle state machine object corresponding to an initiated bus cycle is instantiated and stored in at least one of a plurality of cycle list objects. The combine cycle list stores combinable bus cycles and has number of entries equal to the number of entries in the posted write buffer. A pointer may be placed in the combine list upon creation of each combinable bus cycle. For each combinable cycle stored in it, the initiator cycle list searches the combine list for a cycle with an identical address and byte enable, but a later clock cycle number. This later cycle is matched its data with an appropriate target cycle in the target cycle list. Upon finding the data match, the initiator cycle list resolves the combinable initiator cycle. Thus, false failures due to byte collapsing can be eliminated.
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