发明授权
- 专利标题: Bit line equalize circuit of semiconductor memory device
- 专利标题(中): 半导体存储器件的位线均衡电路
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申请号: US10037申请日: 1998-01-21
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公开(公告)号: US5946251A公开(公告)日: 1999-08-31
- 发明人: Hirotoshi Sato , Yutaka Arita
- 申请人: Hirotoshi Sato , Yutaka Arita
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX9-191458 19970716
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/12 ; G11C11/414 ; G11C11/419 ; G11C11/40
摘要:
A memory cell data is read/written to a memory cell by utilizing the base current of a bipolar transistor having its emitter coupled to a bit line. When activated, a bit line precharge circuit precharges the bit line to a level of a built-in voltage between the emitter and the base of the memory cell bipolar transistor. When bit lines in a pair are lowered in potential from the H level to the L level, the base electrode node potential of the bipolar transistor is never changed to a negative potential by capacitance coupling, and conduction of an access transistor and destruction of memory cell data are prevented. A semiconductor memory device is implemented which does not cause data destruction and can stably operate at high speed even under a low power supply voltage.
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