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US5946251A Bit line equalize circuit of semiconductor memory device 失效
半导体存储器件的位线均衡电路

Bit line equalize circuit of semiconductor memory device
摘要:
A memory cell data is read/written to a memory cell by utilizing the base current of a bipolar transistor having its emitter coupled to a bit line. When activated, a bit line precharge circuit precharges the bit line to a level of a built-in voltage between the emitter and the base of the memory cell bipolar transistor. When bit lines in a pair are lowered in potential from the H level to the L level, the base electrode node potential of the bipolar transistor is never changed to a negative potential by capacitance coupling, and conduction of an access transistor and destruction of memory cell data are prevented. A semiconductor memory device is implemented which does not cause data destruction and can stably operate at high speed even under a low power supply voltage.
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