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    SRAM arrays and methods of manufacturing same
    1.
    发明授权
    SRAM arrays and methods of manufacturing same 有权

    公开(公告)号：US10515688B2

    公开(公告)日：2019-12-24

    申请号：US16404476

    申请日：2019-05-06

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jhon Jhy Liaw

    IPC分类号： G11C11/00 ,  G11C11/414 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H01L27/11 ,  H01L27/02

    摘要： An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of the SRAM array. Each of the first plurality of functional SRAM cells share a first bit line (BL). The SRAM array further includes a second SRAM mini array having a second plurality of functional SRAM cells in the first column. Each of the second plurality of functional SRAM cells share a second BL independently controlled from the first BL. The SRAM array further includes and a SRAM dummy array between the first SRAM mini array and the second SRAM mini array. The SRAM dummy array includes a plurality of SRAM array abut dummy cells in the first column. A first endpoint of the first BL and a second endpoint of the second BL are disposed in the SRAM dummy array.

    Bipolar logic gates on MOS-based memory chips
    2.
    发明授权
    Bipolar logic gates on MOS-based memory chips 有权
    基于MOS的存储芯片上的双极逻辑门

    公开(公告)号：US09583164B2

    公开(公告)日：2017-02-28

    申请号：US14990474

    申请日：2016-01-07

    申请人： Elwha LLC

    发明人： Roderick A. Hyde ,  Jordin T. Kare ,  Lowell L. Wood, Jr.

    IPC分类号： G11C8/10 ,  G11C11/4067 ,  G11C11/414

    CPC分类号： G11C8/10 ,  G11C11/4067 ,  G11C11/414

    摘要： A system uses both MOS-based and bipolar-based decoding circuitry in an address decoder for MOS-based memory. The system includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including MOS-based circuitry and bipolar logic circuitry. The address decoder is configured to accept a word comprising a plurality of bits and access the array of memory cells using the word.

    摘要翻译： 系统在基于MOS的存储器的地址解码器中使用基于MOS和解码电路两者。 该系统包括基于MOS的存储器，其包括被配置为存储数据的多个存储器单元的阵列，以及包括基于MOS的电路和双极逻辑电路的地址解码器。 地址解码器被配置为接受包括多个位的字，并且使用该字访问存储器单元的阵列。

    Full CMOS SRAM cell
    4.
    发明授权
    Full CMOS SRAM cell 有权
    全CMOS SRAM单元

    公开(公告)号：US6445017B2

    公开(公告)日：2002-09-03

    申请号：US72745900

    申请日：2000-12-01

    申请人： SAMSUNG ELECTRONICS CO LTD

    发明人： SONG JUN-EUI

    IPC分类号： G11C11/414 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/10

    CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104 ,  Y10S257/909

    摘要： A full CMOS SRAM cell is provided. The SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed on the semiconductor substrate between the first active region and the second active region parallel to the first active region, and a fourth active region is formed on the semiconductor substrate between the third active region and the second active region parallel to the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, and a second common conductive electrode intersects the second active region and the fourth active region.

    摘要翻译： 提供了一个完整的CMOS SRAM单元。 SRAM单元包括彼此平行布置的形成在半导体衬底上的第一和第二有源区。 第三有源区形成在第一有源区和与第一有源区平行的第二有源区之间的半导体衬底上，并且第四有源区形成在第三有源区和与第二有源区平行的第二有源区之间的半导体衬底上 第二活跃区域。 字线与第一和第二活动区域相交。 第一公共导电电极与第一有源区和第三有源区交叉，第二公共导电电极与第二有源区和第四有源区相交。

    Static semiconductor memory device using bipolar transistor
    6.
    发明授权
    Static semiconductor memory device using bipolar transistor 失效
    使用双极晶体管的静态半导体存储器件

    公开(公告)号：US5216630A

    公开(公告)日：1993-06-01

    申请号：US675628

    申请日：1991-03-26

    申请人： Yasunobu Nakase

    发明人： Yasunobu Nakase

    IPC分类号： G11C11/414 ,  G11C11/411 ,  G11C11/415 ,  G11C11/416 ,  H01L21/8222 ,  H01L21/8229 ,  H01L27/082 ,  H01L27/102

    CPC分类号： G11C11/4116 ,  G11C11/415 ,  G11C11/416

    摘要： Disclosed is a bipolar SRAM including, in each memory cell, two NPN multiemitter transistors, with a base of one transistor being cross-connected to a collector of the other transistor. The respective collectors of these two multiemitter transistors in an arbitrary memory cell are connected to the same positive word line through a load. The first emitter of one of these two multiemitter transistors and the first emitter of the other transistor are connected to the same negative word line. Only when the positive word line corresponding to this negative word line is not selected, a data holding current flows to the negative word line from the first emitter of the transistor having a H level collector potential out of these two multiemitter transistors, and when the corresponding positive word line is selected, the negative word line is controlled not to allow the data holding current to flow. Furthermore, in a data writing, when the arbitrary memory cell is selected in order to reduce or eliminate a current flowing between a second emitter of one transistor of these two multiemitter transistors in the selected memory cell and a bit line connected thereto, the bit line is controlled.

    摘要翻译： 公开了一种双极型SRAM，其在每个存储单元中包括两个NPN多端子晶体管，一个晶体管的基极与另一个晶体管的集电极交叉连接。 任意存储单元中的这两个多端子晶体管的各集电极通过负载连接到相同的正字线。 这两个多端子晶体管之一的第一发射极和另一晶体管的第一发射极连接到相同的负字线。 只有当不选择与该负字线对应的正字线时，数据保持电流从这两个多发射体晶体管中具有H电平集电极电位的晶体管的第一发射极流向负字线，并且当相应的 选择正字线，负字线被控制为不允许数据保持电流流动。 此外，在数据写入中，当选择任意存储单元以减少或消除在所选择的存储单元中的这两个多输出晶体管的一个晶体管的第二发射极与连接的位线之间流动的电流时，位线 被控制。

    Semiconductor memory
    8.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4899314A

    公开(公告)日：1990-02-06

    申请号：US184661

    申请日：1988-04-21

    申请人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    发明人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    IPC分类号： G11C11/414 ,  G11C5/14

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit is provided having first and second level generate circuits producing different levels and first and second emitter follower circuits respectively connected thereto. A level generated by one of the first and second level generate circuits is selectively supplied to either one of the first and second emitter follower circuits. This enables the first and second emitter follower circuits to supply the respective circuits formed in a semiconductor substrate with stable reference voltages.

    摘要翻译： 提供了具有产生不同电平的第一和第二电平发生电路以及分别与其连接的第一和第二射极跟随器电路的半导体集成电路。 由第一和第二电平发生电路之一产生的电平被选择性地提供给第一和第二射极跟随器电路中的任一个。 这使得第一和第二射极跟随器电路能够在半导体衬底中形成的各个电路提供稳定的参考电压。

    Transfer circuit for signal lines
    9.
    发明授权
    Transfer circuit for signal lines 失效
    信号线路传输电路

    公开(公告)号：US4876467A

    公开(公告)日：1989-10-24

    申请号：US291031

    申请日：1988-12-28

    申请人： Atuo Koshizuka

    发明人： Atuo Koshizuka

    IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/414 ,  H03K17/04 ,  H03K17/567

    CPC分类号： G11C7/1006

    摘要： A transfer circuit for signal lines comprises a bipolar transistor and two MIS transistors. A base of the bipolar transistor is connected to a first line of the signal lines, a collector of the bipolar transistor is connected to a power source, the two MIS transistors are connected in series, the connected point is connected to an emitter of the bipolar transistor, and one end of the series-connected MIS transistors is connected to the first line and the other end is connected to a second line of the signal lines. When the first line is transferred to the second line, the MIS transistor connected between the base and emitter of the bipolar transistor is made non-conductive and the other MIS transistor connected to the second line is made conductive. The transfer circuit constituted as above can carry out the transfer of the signal lines at a high speed by rapidly charging the second line.

    Bipolar ram having no write recovery time
    10.
    发明授权
    Bipolar ram having no write recovery time 失效
    双极ram没有写恢复时间

    公开(公告)号：US4864540A

    公开(公告)日：1989-09-05

    申请号：US155022

    申请日：1988-02-11

    申请人： A. David Hashemi ,  Robert M. Reinschmidt

    发明人： A. David Hashemi ,  Robert M. Reinschmidt

    IPC分类号： G11C11/414 ,  G11C11/416

    CPC分类号： G11C11/416

    摘要： A bipolar random access memory having no write recovery time. During a data write operation, while the memory state of the memory cell is being shifted, a data bypass circuit sets a sense latch in the sense amplifier to store the new state to which the memory cell is being set. To prevent the sense latch from being shifted by transient write recovery currents charging bit line parasitic capacitances following the data write operation, a read/write transmission circuit isolates the sense amplifier from the bit lines, diverts current from the sense amplifier to a source of high voltage to charge the parasitic capacitances, and then realigns the sense amplifier to the bit lines.

    摘要翻译： 不具有写恢复时间的双极性随机存取存储器。 在数据写入操作期间，当存储器单元的存储器状态被移位时，数据旁路电路在感测放大器中设置读出锁存器以存储正在设置存储器单元的新状态。 为了防止在数据写入操作之后通过瞬时写入恢复电流对读出锁存器进行充电位线寄生电容的移位，读/写传输电路将读出放大器与位线隔离，将电流从读出放大器转移到高电平 电压对寄生电容进行充电，然后将读出放大器重新对准位线。