A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Addresses are compared with programmed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that programmed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. The clock stopping signal is removed or inhibited when primary or secondary activity is detected or when nap mode is terminated by timeout.