公开(公告)号：US5983355A

公开(公告)日：1999-11-09

申请号：US650355

申请日：1996-05-20

申请人： John D. Kenny ,  Emilia Lei ,  Vimi Pandey

发明人： John D. Kenny ,  Emilia Lei ,  Vimi Pandey

IPC分类号： G06F1/00

CPC分类号： G06F1/00

摘要： A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Addresses are compared with fixed software interrupt addresses. Matching non-prefetched addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be throttled until a programmable NAP timer expires. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity may occur. A prefetch detect circuit ensures that fixed software interrupt addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. The clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap mode is terminated by a nap timer timing out.

摘要翻译： 公开了一种用于控制处理器中的时钟停止信号的应用以限制功耗的方法和装置。 系统控制器接收地址，指示主要和次要系统活动的信号，以及至少一个休眠超时信号。 地址与固定软件中断地址进行比较。 匹配非预取地址触发睡眠模式。 在小睡模式触发时，可以限制时钟停止信号，直到可编程NAP定时器期满。 在节流期间应用具有可编程占空比的时钟停止信号，可确保检测和维修主要和次要活动所需的处理。 预取检测电路确保在预取中间加载的固定软件中断地址不触发时钟停止信号。 当检测到主要或次要活动时，或者当睡眠定时器超时终止睡眠模式时，时钟停止信号被去除或禁止。

公开(公告)号：US5954819A

公开(公告)日：1999-09-21

申请号：US649557

申请日：1996-05-17

申请人： John D. Kenny ,  Kenneth Ma ,  Vimi Pandey

发明人： John D. Kenny ,  Kenneth Ma ,  Vimi Pandey

IPC分类号： G06F1/32 ,  G06F11/34 ,  G06F1/00

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F11/3423 ,  Y02B60/1221 ,  Y02B60/165 ,  Y02B60/32

摘要： A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Addresses are compared with programmed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that programmed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. The clock stopping signal is removed or inhibited when primary or secondary activity is detected or when nap mode is terminated by timeout.

摘要翻译： 公开了一种用于控制处理器中的时钟停止信号的应用以限制功耗的方法和装置。 系统控制器接收地址，指示主要和次要系统活动的信号，以及至少一个休眠超时信号。 地址与编程地址进行比较。 匹配地址触发睡眠模式。 在小睡模式触发时，可以在节流期间施加时钟停止信号。 在节流期间应用具有可编程占空比的时钟停止信号，可确保对主要和次要活动进行检测和维修所需的处理。 预取检测电路确保在预取中间加载的编程地址不会触发时钟停止信号。 当检测到主要或次要活动或当休眠模式由超时终止时，时钟停止信号被去除或禁止。

公开(公告)号：US5983356A

公开(公告)日：1999-11-09

申请号：US665778

申请日：1996-06-18

申请人： Vimi Pandey ,  Kenneth Ma ,  Leo Jiang ,  Scott Shaw

发明人： Vimi Pandey ,  Kenneth Ma ,  Leo Jiang ,  Scott Shaw

IPC分类号： G06F1/32 ,  G06F1/00 ,  G06F1/04 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  Y02B60/144

摘要： A method and apparatus is disclosed for controlling the application of a clock stopping signal in a processor to limit power consumption. The system controller receives addresses, signals indicative of primary and secondary system activity, and at least one nap timeout signal. Interrupt addresses or programmed addresses are trapped and stored as shadowed addresses. Current addresses may be compared with shadowed addresses. Matching addresses trigger a nap mode. Upon nap mode triggering, the clock stopping signal may be applied during a throttling period. Applying the clock stopping signal with programmable duty cycle during the throttling period ensures that processing necessary for the detection and servicing of primary and secondary activity can occur. A prefetch detect circuit ensures that shadowed addresses loaded in the middle of a prefetch do not trigger the clock stopping signal. Clock stopping signal is removed or inhibited when primary or secondary activity is detected or when a nap timer expires.

摘要翻译： 公开了一种用于控制处理器中的时钟停止信号的应用以限制功耗的方法和装置。 系统控制器接收地址，指示主要和次要系统活动的信号，以及至少一个休眠超时信号。 中断地址或编程地址被捕获并存储为阴影地址。 当前地址可能与阴影地址进行比较。 匹配地址触发睡眠模式。 在小睡模式触发时，可以在节流期间施加时钟停止信号。 在节流期间应用具有可编程占空比的时钟停止信号，可确保对主要和次要活动进行检测和维修所需的处理。 预取检测电路确保预取中间加载的阴影地址不会触发时钟停止信号。 当检测到主要或次要活动时或当小时计时器到期时，时钟停止信号被去除或禁止。