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US5964883A Arrangement and method for handling bus clock speed variations 失效
处理总线时钟速度变化的布置和方法

Arrangement and method for handling bus clock speed variations
Abstract:
An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating a different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.
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