Arrangement and method for handling bus clock speed variations
    1.
    发明授权
    Arrangement and method for handling bus clock speed variations 失效
    处理总线时钟速度变化的布置和方法

    公开(公告)号:US5964883A

    公开(公告)日:1999-10-12

    申请号:US754206

    申请日:1996-11-20

    Abstract: An arrangement for monitoring clock frequency variations on a peripheral bus is provided to improve operations of the peripheral device despite changes in the clock frequency. In one aspect of the arrangement, a processing unit is coupled to a host bus which in turn is coupled to a peripheral bus which is coupled to a peripheral device. A monitoring arrangement is provided which detects a change in the clock frequency of the peripheral bus and determines if the frequency change exceeds a threshold associated with the peripheral device. If the threshold is exceeded, the peripheral device is informed that the clock frequency of the peripheral bus has changed. A peripheral device operating a different operating levels may use the information from the monitoring arrangement to alter the operating level of the peripheral device to conform to the new bus clock frequency.

    Abstract translation: 提供用于监视外围总线上的时钟频率变化的布置,以改善外围设备的操作,尽管时钟频率发生变化。 在该配置的一个方面,处理单元耦合到主机总线,主机总线又耦合到耦合到外围设备的外围总线。 提供了一种监视装置,其检测外围总线的时钟频率的变化,并确定频率变化是否超过与外围设备相关联的阈值。 如果超过阈值,则通知外围设备外围总线的时钟频率已经改变。 操作不同操作级别的外围设备可以使用来自监视装置的信息来改变外围设备的操作级别以符合新的总线时钟频率。

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