A superscalar microprocessor implements instruction level patching. A instruction fetch unit includes a register for storing opcodes of instructions to be patched. When an instruction is fetched, the instruction fetch unit compares the opcode of the fetched instruction to the opcode stored in the patch opcode register. If the opcode of the fetched instruction matches an opcode stored in the patch opcode register, the instruction is dispatched to a microcode instruction unit. The microcode instruction unit invokes a patch microcode routine that dispatches a plurality of microcode instruction that causes a substitute microcode instruction stored in external memory to be loaded into patch data registers. The microcode instruction unit then dispatches the substitute instruction stored in the patch data registers and the substitute instruction is executed by a functional unit in place of the original instruction.