The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I.sub.2) supplied by a reference transistor (R) to a first current (I.sub.1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.