发明授权
US5994176A Method for forming self-aligned silicided MOS transistors with
asymmetric ESD protecting transistors
失效
用于形成具有非对称ESD保护晶体管的自对准硅化MOS晶体管的方法
- 专利标题: Method for forming self-aligned silicided MOS transistors with asymmetric ESD protecting transistors
- 专利标题(中): 用于形成具有非对称ESD保护晶体管的自对准硅化MOS晶体管的方法
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申请号: US25971申请日: 1998-02-19
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公开(公告)号: US5994176A公开(公告)日: 1999-11-30
- 发明人: Shye-Lin Wu
- 申请人: Shye-Lin Wu
- 申请人地址: TWX Hsinchu
- 专利权人: Texas Instruments - Acer Incorporated
- 当前专利权人: Texas Instruments - Acer Incorporated
- 当前专利权人地址: TWX Hsinchu
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234 ; H01L21/8242 ; H01L27/02 ; H01L21/8238
摘要:
The method of forming a MOS transistor in a semiconductor substrate with the self-aligned silicide contact for ESD protection includes the following steps. At first, an isolation region is formed to separate an ESD protective region and a functional region. A gate insulator layer and a polysilicon layer are formed. The polysilicon layer is then patterned to form a gate structure. The substrate is doped to form a lightly doped region and the ESD protective region is then doped to have a junction region. A covering layer is then formed over the ESD protective region and a first dielectric layer is formed. A portion of the first dielectric layer is removed to form a spacer structure. A silicidation process is performed to form a metal silicide layer and the metal silicide layer is then doped. A second dielectric layer is formed and a thermal process is then performed to form a junction region in the functional region.
公开/授权文献
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