A wiring layer 36A is formed by sputtering, reflowing and patterning of an Al alloy layer on insulating layers 32 and 34 covering the surface of a semiconductor substrate 30. A silicon oxide layer 38 is formed by coating a hydrogen silsesquioxane resin film flatly over the layer 36A and by successive heat treatment. Then a silicon oxide layer 40 is formed on the layer 38 by plasma-enhanced chemical vapor deposition. After formation of the desired connecting hole in an interlayer insulating layer made of a lamination of the layers 38 and 40, a wiring layer 46 connected with the layer 36A via the connecting hole is formed by sputtering, reflowing and patterning of an Al alloy layer. Results of the measurements of the resistance of the via chains having 20000 vias indicated that resistace rise has not been observed. A multi-layered wiring which is highly resistant to stress migration is provided.