公开(公告)号：US08164160B2

公开(公告)日：2012-04-24

申请号：US12155232

申请日：2008-05-30

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L29/92

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0805 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.

摘要翻译： 根据本发明的半导体器件具有多层布线结构，其层叠并设置多个夹着绝缘膜的多层布线结构，并且包括：以铜为主要成分的铜线; 形成在铜线上的绝缘膜; 铝线，其以铝为主要成分，并形成在所述绝缘膜上，以通过形成为穿透所述绝缘膜的通孔与所述铜线电连接; 和形成在铝线上的表面保护膜; 并且所述表面保护膜形成有用于使铝线的一部分暴露于与外部部分电连接的电极焊盘的焊盘开口。

公开(公告)号：US20100190335A1

公开(公告)日：2010-07-29

申请号：US12659602

申请日：2010-03-15

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76855 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device according to the present invention, a wiring trench is formed on the surface of an insulating film, and the inner surface of this wiring trench is thereafter coated with an alloy film made of an alloy material containing copper and a prescribed metallic element. After this coating with the alloy film, a copper film is laminated on the insulating film to fill up the wiring trench. Then, unnecessary portions of the copper film outside the wiring trench are removed, so that the surface of the copper film remaining in the wiring trench is generally flush with the surface of the insulating film. Thereafter heat treatment is performed. The prescribed metallic element is deposited on the wiring trench due to this heat treatment. Then, the prescribed metallic element deposited on the wiring trench is removed.

摘要翻译： 在制造本发明的半导体器件的方法中，在绝缘膜的表面上形成布线沟槽，然后用由含铜的合金材料制成的合金膜涂覆该布线沟槽的内表面， 规定的金属元素。 在用合金膜涂覆之后，在绝缘膜上层压铜膜以填充布线沟槽。 然后，除去布线沟槽外部的铜膜的不必要部分，使得残留在布线沟槽中的铜膜的表面与绝缘膜的表面大致齐平。 然后进行热处理。 由于这种热处理，规定的金属元素沉积在布线沟槽上。 然后，去除沉积在布线沟槽上的规定金属元素。

公开(公告)号：US20080296772A1

公开(公告)日：2008-12-04

申请号：US12155231

申请日：2008-05-30

申请人： Yuichi Nakao ,  Takahisa Yamaha

发明人： Yuichi Nakao ,  Takahisa Yamaha

IPC分类号： H01L23/48

CPC分类号： H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/11 ,  H01L28/60 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005 ,  H01L2924/01004

摘要： A semiconductor device according to the present invention includes: a lower wire having copper as a main component; an insulating film formed on the lower wire; an upper wire formed on the insulating film; a tungsten plug penetrating through the insulating film and formed of tungsten for electrically connecting the lower wire and the upper wire; and a barrier layer interposed between the lower wire and the tungsten plug; and the barrier layer including a tantalum film contacting the lower wire and a titanium nitride film contacting the tungsten plug.

摘要翻译： 根据本发明的半导体器件包括：以铜为主要成分的下线; 形成在下线上的绝缘膜; 形成在绝缘膜上的上部线; 穿过绝缘膜并由钨形成的用于电连接下线和上线的钨塞; 以及插入在所述下线和所述钨插塞之间的阻挡层; 并且阻挡层包括接触下线的钽膜和与钨插塞接触的氮化钛膜。

公开(公告)号：US06541373B2

公开(公告)日：2003-04-01

申请号：US09978598

申请日：2001-10-16

申请人： Takahisa Yamaha

发明人： Takahisa Yamaha

IPC分类号： H01L214763

CPC分类号： H01L21/02134 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3124 ,  H01L21/316 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/3171 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state. After a wiring layer is formed on the insulating film, a silicon oxide film as a surface protection film is formed on the insulating film, covering the wiring layer. In order to reduce process damages, heat treatment is performed 30 minutes at 400° C. in a nitrogen gas atmosphere. With this heat treatment, hydrogen in the silicon oxide film is released and diffuses into the channel region of the transistor to lower interfacial energy levels. Since the silicon nitride film does not transmit hydrogen, it is not necessary for the heat treatment atmosphere to contain hydrogen. A variation in threshold voltages of MOS type transistors can be easily lowered.

公开(公告)号：US06251805B1

公开(公告)日：2001-06-26

申请号：US08993681

申请日：1997-12-18

申请人： Takahisa Yamaha ,  Yushi Inoue

发明人： Takahisa Yamaha ,  Yushi Inoue

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31051 ,  H01L21/3124 ,  H01L21/316

摘要： A hydrogen silsesquloxane resin film is formed flat by spin-coating or another such method on the surface of a semiconductor substrate or another such treatment wafer 38, after which the above-mentioned resin film is subjected to a heat treatment in an inert gas atmosphere to form a silicon oxide film of preceramic phase. In a hot plate type of heating apparatus, the wafer 38 is placed on a conveyor belt 34 and moved above a heat-generating block 30, which heats the wafer in the open air and converts the preceramic-phase silicon oxide film into a ceramic-phase silicon oxide film. The silane generated during heating does not adhere to the wafer surface as SiO2 particles, so no microscopic protrusions are produced. N2 or another such inert gas may be blown at the wafer 38 during heating.

摘要翻译： 在半导体基板或另一个这样的处理晶片38的表面上，通过旋涂或其他这种方法将氢硅倍半酚树脂膜平坦地形成，之后将上述树脂膜在惰性气体气氛中进行热处理 形成前陶瓷相的氧化硅膜。 在热板式加热装置中，将晶片38放置在输送带34上并移动到发热块30上方，该发热块30在露天加热晶片，并将陶瓷前氧化硅膜转换为陶瓷 - 相氧化硅膜。 在加热过程中产生的硅烷作为SiO 2颗粒不粘附到晶片表面，因此不产生微观突起。 在加热期间，可以在晶片38上吹入N 2或另一种这样的惰性气体。

公开(公告)号：US6150720A

公开(公告)日：2000-11-21

申请号：US223534

申请日：1998-12-30

申请人： Takahisa Yamaha ,  Tetsuya Kuwajima

发明人： Takahisa Yamaha ,  Tetsuya Kuwajima

IPC分类号： C23C14/06 ,  C23C14/34 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H07L23/532

CPC分类号： H01L21/76846 ,  H01L21/7684 ,  H01L21/76843 ,  Y10S257/915

摘要： In a wiring forming method according to the present invention, an insulating layer is formed on a semiconductor substrate, and contact holes are formed in the insulating layer. A titanium layer is deposited on the insulating layer so as to be along inner surfaces of the contact holes. A first titanium nitride layer is formed on the titanium layer including the titanium layer formed in the contact holes. The deposition of the first titanium nitride layer is carried out under atmosphere which substantially includes no oxygen. A titanium oxynitride layer is deposited on the first titanium nitride layer. A second titanium nitride layer is deposited on the titanium oxynitride layer. Buried plugs are formed on the second titanium nitride layer formed in the contact holes. A wiring connected to the buried plugs are formed on the insulating layer. A barrier metal layer and the buried plugs are thus formed in the contact holes. According to such the structure, a stable electric contact can be obtained.

摘要翻译： 在根据本发明的布线形成方法中，在半导体衬底上形成绝缘层，并且在绝缘层中形成接触孔。 在绝缘层上沉积钛层以沿接触孔的内表面。 在包括形成在接触孔中的钛层的钛层上形成第一氮化钛层。 第一氮化钛层的沉积在基本上不包含氧的气​​氛下进行。 氧氮化钛层沉积在第一氮化钛层上。 第二氮化钛层沉积在氮氧化钛层上。 在形成在接触孔中的第二氮化钛层上形成埋置的塞子。 在绝缘层上形成连接到埋地塞的布线。 因此，在接触孔中形成阻挡金属层和掩埋塞。 根据这样的结构，可以获得稳定的电接触。

公开(公告)号：US5885857A

公开(公告)日：1999-03-23

申请号：US7619

申请日：1998-01-15

申请人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

发明人： Takahisa Yamaha ,  Yushi Inoue ,  Masaru Naito

IPC分类号： H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L21/283 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L23/3171 ,  H01L2924/0002

摘要： A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

摘要翻译： 一种树脂模制半导体器件，其具有布线层和包括SOG膜的层间绝缘层，能够抑制由于热应力引起的SOG膜中的裂纹的产生。 在半导体芯片的外周区域中，在包括SOG膜的层间绝缘层中形成通孔，以显着减少残留的SOG膜。 作为包含SOG膜的层间绝缘层的下层，形成虚拟布线图案，以使虚拟布线图案上的SOG膜变薄。 也可以通过使用较高级布线层，埋入通孔并接触下层虚拟布线图案来形成虚拟布线图案。

公开(公告)号：US5705429A

公开(公告)日：1998-01-06

申请号：US467846

申请日：1995-06-06

申请人： Takahisa Yamaha ,  Satoshi Hibino ,  Masaru Naito

发明人： Takahisa Yamaha ,  Satoshi Hibino ,  Masaru Naito

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76877 ,  H01L21/2855

摘要： After forming a contact hole in an insulator layer, which is formed on a substrate covering an impurity doped region, a Ti film, a TiN film (or TiON film), and an Al alloy (for example, an alloy of Al--Si--Cu) layer are sputtered (consecutively from the bottom level) for forming a wiring material layer. A wiring layer is formed by patterning the wiring material layer in accordance with a wiring pattern. Portions with a 0% coverage of the Al alloy layer are eliminated by sputtering the Al alloy layer with a substrate temperature in a range between 100.degree.and 150.degree. C.

摘要翻译： 在形成在覆盖杂质掺杂区域的基板上的绝缘体层中形成接触孔，Ti膜，TiN膜（或TiON膜）和Al合金（例如，Al-Si- Cu）层（从底层连续地）溅射以形成布线材料层。 通过根据布线图案图案化布线材料层而形成布线层。 Al合金层的覆盖率为0％的部分通过溅射Al合金层，基板温度在100〜150℃的范围内。

公开(公告)号：US5428251A

公开(公告)日：1995-06-27

申请号：US227685

申请日：1994-04-14

申请人： Masaru Naito ,  Takahisa Yamaha

发明人： Masaru Naito ,  Takahisa Yamaha

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/417

CPC分类号： H01L23/53214 ,  H01L2924/0002

摘要： In a multi-layer wiring structure of an integrated circuit device, occurrence of voids due to electromigration in the vicinity of an interface between upper and lower wiring layers is suppressed. The interface is cleaned in vacuum and grain size of the wiring layers is controlled. After an interlayer insulating film (16) having a connection hole (16A) is formed to cover a first wiring layer (14) of Al or an Al alloy, a second wiring layer (18) of Al or an Al alloy is formed and connected to the first wiring layer through the connection hole. When the second wiring layer is formed, grains (G.sub.2) of the second wiring layer are formed so as to be :respectively continuously adjacent to and substantially equal in size to grains (G.sub.1) of the first wiring layer which appear at the interface. This control may be done by suitably controlling the condition of sputter-etching the surface of the first wiring layer through the connection hole and the condition of sputtering the Al or Al alloy of tile second wiring layer.

摘要翻译： 在集成电路器件的多层布线结构中，抑制了由于上下布线层之间的界面附近的电迁移引起的空隙的发生。 界面在真空中清洁，并且控制布线层的晶粒尺寸。 在形成具有连接孔（16A）的层间绝缘膜（16）以覆盖Al或Al合金的第一布线层（14）之后，形成并连接Al或Al合金的第二布线层（18） 通过连接孔到第一布线层。 当第二布线层形成时，第二布线层的晶粒（G2）形成为分别连续地邻近于并且基本上等于出现在界面处的第一布线层的晶粒（G1）。 该控制可以通过适当地控制通过连接孔溅射蚀刻第一布线层的表面的条件和溅射第二布线层的Al或Al合金的条件来进行。

公开(公告)号：US5036382A

公开(公告)日：1991-07-30

申请号：US482566

申请日：1990-02-21

申请人： Takahisa Yamaha

发明人： Takahisa Yamaha

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/43

CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L2924/0002

摘要： A multi level wiring structure incorporated in a semiconductor device has a wiring layer sandwiched between insulating films and coupled to upper and lower conduction paths through contact windows formed in the insulating films, respectively, and the wiring layer is implemented by an aluminum-silicon alloy film sandwiched between upper and lower barrier films formed of a conductive substance selected from the group consisting of a refractory metal silicide, a refractory metal and a refractory metal alloy, and the barrier films are operative to prevent undesirable recrystallized silicon precipitates from direct contacting the upper and lower conduction paths, so that the wiring layer is kept well conductive with respect to the upper and lower conduction paths.

摘要翻译： 结合在半导体器件中的多层布线结构具有夹在绝缘膜之间的布线层，并分别通过形成在绝缘膜中的接触窗与上下导电路径耦合，并且布线层由铝 - 硅合金膜 夹在由难熔金属硅化物，难熔金属和耐火金属合金组成的组中的导电物质形成的上阻挡膜和下阻挡膜之间，并且阻挡膜用于防止不期望的重结晶硅沉淀物直接接触上和 下导电路径，使得布线层相对于上导电路径和下导电路径保持良好的导电性。