A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from relatively global conductors on the device or from data inputs to the region. The control signals allow synchronous or asynchronous clearing of a register in each subregion. The control signals also allow synchronous loading of the register in each subregion, and the data loaded can be either one of the data inputs to the subregion (so-called lonely register operation) or a signal produced by the logic of the subregion.