发明授权
- 专利标题: Clock enable/disable circuit of power management system
- 专利标题(中): 电源管理系统的时钟使能/禁止电路
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申请号: US9848申请日: 1998-01-20
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公开(公告)号: US6021501A公开(公告)日: 2000-02-01
- 发明人: Michael John Shay
- 申请人: Michael John Shay
- 申请人地址: CA Santa Clara
- 专利权人: National Semiconductor Corporation
- 当前专利权人: National Semiconductor Corporation
- 当前专利权人地址: CA Santa Clara
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F1/06 ; G06F1/08 ; G06F1/24 ; G06F1/32 ; H03L3/00 ; G06F1/10
摘要:
A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interle circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering. A bypassing circuit enables the clock stabilization filter when the external oscillator is a crystal oscillator and for bypassing the clock stabilization filter when the external oscillator is a can oscillator. A masking circuit masks the oscillations from the rest of the power management system. The masking circuit has circuitry which disables the clock masking after a falling edge of the oscillations and stats back up with a rising transition of the oscillations.
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