Invention Grant
US06021564A Method for reducing via inductance in an electronic assembly and article
有权
减少电子组件和制品中的通孔电感的方法
- Patent Title: Method for reducing via inductance in an electronic assembly and article
- Patent Title (中): 减少电子组件和制品中的通孔电感的方法
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Application No.: US159140Application Date: 1998-09-23
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Publication No.: US06021564APublication Date: 2000-02-08
- Inventor: David A. Hanson
- Applicant: David A. Hanson
- Applicant Address: DE Newark
- Assignee: W. L. Gore & Associates, Inc.
- Current Assignee: W. L. Gore & Associates, Inc.
- Current Assignee Address: DE Newark
- Main IPC: H01L23/12
- IPC: H01L23/12 ; H01L21/48 ; H01L23/498 ; H01L23/538 ; H01L23/66 ; H05K1/11 ; H01K3/10
Abstract:
A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.
Information query
IPC分类: