Single layer poly fabrication method and device with shallow
emitter/base junctions and optimized channel stopper
    5.
    发明授权
    Single layer poly fabrication method and device with shallow emitter/base junctions and optimized channel stopper 失效
    单层多晶制造方法和具有浅发射极/基极结和优化的通道阻塞的装置

    公开(公告)号:US4721685A

    公开(公告)日:1988-01-26

    申请号:US853792

    申请日:1986-04-18

    CPC classification number: H01L21/31654 H01L21/033 H01L21/76216

    Abstract: A method for fabricating high performance bipolar transistors using a single polycrystalline silicon layer whereby horizontally and vertically scaled base/emitter junctions are achieved. In an extrinsic base transistor, a composite sandwich of overlying layers of poly silicon, oxide and nitride are deposited over a substrate containing field oxide isolated monocrystalline transistor sites having buried subcollectors and sinker regions. The composite sandwich is thereafter selectively oxidized to define base, emitter and collector regions with the relative thickness of the composite sandwich and the grown oxide being controlled to assure proper horizontal extrinsic base to emitter spacings and shallow vertical intrinsic base to emitter junctions, upon completing subsequent implant and annealing steps. Each active transistor site is also surrounded by a ring-like, channel stopper which is physically isolated from the channel stopper of each other device.

    Abstract translation: 一种用于制造使用单个多晶硅层的高性能双极晶体管的方法,从而实现水平和垂直缩放的基极/发射极结。 在外部基极晶体管中,在包含具有掩埋子集电极和沉降区的场氧化物隔离的单晶晶体管位置的衬底上沉积多晶硅,氧化物和氮化物的覆盖层的复合夹层。 然后,复合夹心物被选择性地氧化以限定具有复合夹心物的相对厚度的基底,发射极和集电极区域,并且生长的氧化物被控制以确保随后完成的适当的水平外在基极与发射极间隔和浅垂直本征基极到发射极结 植入和退火步骤。 每个有源晶体管的位置也被一个环形的通道阻挡器所围绕,该阻挡器与每个其它装置的通道阻塞物理隔离。

    Spinal Implant
    7.
    发明申请
    Spinal Implant 审中-公开
    脊柱植入

    公开(公告)号:US20080188940A1

    公开(公告)日:2008-08-07

    申请号:US11767673

    申请日:2007-06-25

    Abstract: A spinal implant is provided that includes a body having at least one piece of cortical bone. The body has a tapered leading end, a trailing end and first and second sides. The body also includes superior and inferior surfaces that are inclined relative to one another. A first plurality of grooves is formed in the superior surface and a second plurality of the grooves is formed in the inferior surface. Each groove of the first and second pluralities of the grooves has first and second opposing faces converging toward and intersecting one another. Each groove has a maximum cross-sectional width. Each adjacent pair of the grooves of the first and second pluralities of the grooves is separated by a generally planar portion of the superior and inferior surfaces, respectively. Each of the generally planar portions has a width that is equal to or greater than the maximum cross-sectional width of each of the grooves of the respective adjacent pair of the grooves.

    Abstract translation: 提供脊柱植入物,其包括具有至少一片皮质骨的主体。 主体具有锥形前端,后端以及第一和第二侧。 身体还包括相对于彼此倾斜的上下表面。 在上表面上形成有第一多个槽,在下表面形成第二多个槽。 第一和第二多个凹槽中的每个凹槽具有朝向彼此并且相交的第一和第二相对面。 每个槽具有最大横截面宽度。 第一和第二多个凹槽中的每个相邻的一对凹槽分别由上表面和下表面的大致平面部分分开。 每个大致平坦的部分具有等于或大于相应的相邻槽对中的每个槽的最大横截面宽度的宽度。

    Clock start up stabilization for computer systems
    8.
    发明授权
    Clock start up stabilization for computer systems 失效
    计算机系统的时钟启动稳定

    公开(公告)号:US5355397A

    公开(公告)日:1994-10-11

    申请号:US950628

    申请日:1992-09-24

    CPC classification number: G06F1/10 H03K5/13

    Abstract: Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

    Abstract translation: 诸如逻辑芯片电路之类的利用电路被阻止接收在主系统时钟启动之后产生的一串时钟脉冲的初始一个或多个脉冲,而此后发生的该列的脉冲被耦合到利用电路。 这防止了相对于随后的列车脉冲在列车的初始脉冲之间通常存在的偏斜不利地影响利用电路的操作。 尽管该系统可适应于允许预选这些吞咽脉冲的数目,吞咽这个时钟优选地阻止某些预定数量的初始时钟脉冲到达电路的其余部分。

    Clock distribution apparatus and processes particularly useful in
multiprocessor systems
    9.
    发明授权
    Clock distribution apparatus and processes particularly useful in multiprocessor systems 失效
    时钟分配装置和处理在多处理器系统中特别有用

    公开(公告)号:US5293626A

    公开(公告)日:1994-03-08

    申请号:US536270

    申请日:1990-06-08

    CPC classification number: G06F1/10 G06F1/105 H04J3/0626

    Abstract: Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse and fine selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.

    Abstract translation: 来自主振荡器的时钟脉冲被分布在多处理器计算机系统中,使得它们在彼此极其紧密的时间容限内到达位于模块的操作簇中的大量利用点。 通过直接测量或通过使用已知的标准特性来确定与每个组件,电气或光学连接,电缆等相关联的延迟。 对从主时钟源到最终芯片传送点的初始发散点的每个完整时钟脉冲路径的延时预算进行记录和求和。 能够引入预定量的时间延迟的组件被并入一些或所有时钟脉冲路径中。 调整这些组件以平衡从时钟路径预算确定的差异。 时钟路径单独地或与光学组件组合地实现在电气部件中,或者在基本上所有的光学配置中实现。 用于控制光学偏斜的一种布置包括可以相对于彼此在同轴方向物理上移位的光学元件的布置。 倾斜调整网络采用由电气部件,光学部件或其组合实现的粗略和精细可选延迟阵列的独特组合。

    Dynamic property data integration framework

    公开(公告)号:US10360188B2

    公开(公告)日:2019-07-23

    申请号:US13560810

    申请日:2012-07-27

    Abstract: A dynamic integration framework allows property data to be dynamically influenced by external data sources. In one example, a client services component receives, from a client application, a request to create or edit an object. The client services component retrieves, from a content repository, an initial property set applicable to the object. An external data service specifies an initial property modification set based on property dependencies between controlling property values and dependent properties. The external data service provides the property modifications to the client services component with an initial data identifier that indicates a state of the property modifications. The client services component merges the initial property modifications and the initial data identifier with the initial property set.

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