Invention Grant
- Patent Title: Method for verifying hold time in integrated circuit design
- Patent Title (中): 验证集成电路设计中的保持时间的方法
-
Application No.: US841839Application Date: 1997-05-05
-
Publication No.: US6023767APublication Date: 2000-02-08
- Inventor: Sudarshan Kumar , James J. C. Lan , Rajesh Manglore
- Applicant: Sudarshan Kumar , James J. C. Lan , Rajesh Manglore
- Applicant Address: CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: CA Santa Clara
- Main IPC: G06F1/10
- IPC: G06F1/10 ; G06F1/04
Abstract:
A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.
Public/Granted literature
- US4725130A Zoom finder Public/Granted day:1988-02-16
Information query