The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode. Hemispherical grained silicon (HSG-Si) is deposited on the surface of the patterned polysilicon layer and an etch back process is used to transfer the topology of the HSG-Si layer to the underlying polysilicon. Further processing provides a capacitor dielectric and an upper electrode.