A sense amplifier circuit for a semiconductor memory device. The sense amplifier of this invention has four more NMOS transistors than a conventional amplifier. The gate terminals of two of the NMOS transistors are connected to a write enable line. The gate terminals of the other two NMOS transistors are connected to a first and a second node point, which are in turn connected to a bit line and a complementary bit line, respectively. Through a feedback circuit provided by these four additional NMOS transistors, two of the NMOS transistors are switched on during a write cycle to provide a ground connection so that voltage level of the sense amplifier is rapidly pulled down. Since the latching speed of the sense amplifier is increased, the operating speed of the memory is increased, as well. In addition, partial writing of data can be avoided.