公开(公告)号：US6031776A

公开(公告)日：2000-02-29

申请号：US376750

申请日：1999-08-17

申请人： Juei-Lung Chen ,  Hsin-Pang Lu

发明人： Juei-Lung Chen ,  Hsin-Pang Lu

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/065

摘要： A sense amplifier circuit for a semiconductor memory device. The sense amplifier of this invention has four more NMOS transistors than a conventional amplifier. The gate terminals of two of the NMOS transistors are connected to a write enable line. The gate terminals of the other two NMOS transistors are connected to a first and a second node point, which are in turn connected to a bit line and a complementary bit line, respectively. Through a feedback circuit provided by these four additional NMOS transistors, two of the NMOS transistors are switched on during a write cycle to provide a ground connection so that voltage level of the sense amplifier is rapidly pulled down. Since the latching speed of the sense amplifier is increased, the operating speed of the memory is increased, as well. In addition, partial writing of data can be avoided.

摘要翻译： 一种用于半导体存储器件的读出放大器电路。 本发明的读出放大器具有比常规放大器多四个NMOS晶体管。 两个NMOS晶体管的栅极端子连接到写使能线。 另外两个NMOS晶体管的栅极端子连接到第一和第二节点，它们又分别连接到位线和互补位线。 通过由这四个附加NMOS晶体管提供的反馈电路，在写周期期间，两个NMOS晶体管导通，以提供接地连接，使得读出放大器的电压电平被快速下拉。 由于读出放大器的锁存速度增加，因此存储器的操作速度也增加。 此外，可以避免部分写入数据。

公开(公告)号：US6108258A

公开(公告)日：2000-08-22

申请号：US378241

申请日：1999-08-19

申请人： Juei-Lung Chen ,  Shin-Huang Huang ,  Hsin-Pang Lu

发明人： Juei-Lung Chen ,  Shin-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C7/06 ,  G11C7/02

CPC分类号： G11C7/062 ,  G11C7/065

摘要： A sense amplifier can be used with a high-speed IC memory device, which sense amplifier can help reduce the sensing latency during read operations to the memory device so as to allow fast access speed to the memory device. The sense amplifier includes a first-stage circuit, coupled to the bit lines of the memory device, for amplifying the differential data signal on the bit lines. Furthermore, a second-stage circuit has an input side coupled to receive the output signal from the first-stage circuit and an output side coupled to the bit lines, and is used for amplifying the output signal from the first-stage circuit and feeding the amplified signal back to the bit lines. The first-stage circuit and the second-stage circuit in combination constitute a positive feedback amplification loop coupled to the bit lines for amplifying the differential data signal on the bit lines to a detectable level. This positive feedback amplification loop allows the differential data signal on the bit lines to be quickly amplified to the detectable level with a reduced sensing latency, thus increasing the access speed to the associated memory device. Moreover, even though the bit lines are increased in length, the sensing speed is not significantly affected. This feature can also help save circuit layout space.

摘要翻译： 感测放大器可以与高速IC存储器件一起使用，该读出放大器可以帮助减少对存储器件的读取操作期间的感测延迟，以便允许对存储器件的快速存取速度。 读出放大器包括耦合到存储器件的位线的第一级电路，用于放大位线上的差分数据信号。 此外，第二级电路的输入端被耦合以接收来自第一级电路的输出信号和耦合到位线的输出端，并且用于放大来自第一级电路的输出信号并将 放大信号回到位线。 第一级电路和第二级电路组合构成耦合到位线的正反馈放大环路，用于将位线上的差分数据信号放大到可检测电平。 该正反馈放大环路允许位线上的差分数据信号以较小的感测等待时间被快速放大到可检测电平，从而增加到相关存储器件的访问速度。 此外，即使位线的长度增加，感测速度也不会受到很大的影响。 此功能还可以帮助节省电路布局空间。

公开(公告)号：US6037759A

公开(公告)日：2000-03-14

申请号：US392879

申请日：1999-09-09

申请人： Juei-Lung Chen ,  Hsin-Pang Lu

发明人： Juei-Lung Chen ,  Hsin-Pang Lu

IPC分类号： G05F1/44 ,  G05F1/46

CPC分类号： G05F1/46

摘要： A voltage regulator capable of improving system response. The voltage regulator includes a feedback circuit and an operational amplifier. The input terminal of the feedback circuit is coupled to an output voltage terminal for attenuating signals coming out of the output terminal. The operational amplifier comprises a pre-amplifier, a clamping circuit and a power amplifier, all serially connected together. The input terminals of the pre-amplifier are respectively coupled to the output terminal of the feedback circuit and an input voltage terminal. The pre-amplifier is a device for amplifying differential voltage between input voltage signals and feedback voltage signals. The clamping circuit is a device for clamping amplified differential voltage from the pre-amplifier between a pre-defined voltage range. The power amplifier is a device for increasing the power of the differential voltage signals. The invention is able to maintain a quick response from the operational amplifier without reducing the frequency bandwidth of the amplifier.

摘要翻译： 能够提高系统响应的电压调节器。 电压调节器包括反馈电路和运算放大器。 反馈电路的输入端子耦合到输出电压端子，用于衰减从输出端子出来的信号。 运算放大器包括前置放大器，钳位电路和功率放大器，全部串联连接在一起。 前置放大器的输入端分别耦合到反馈电路的输出端和输入电压端。 前置放大器是用于放大输入电压信号和反馈电压信号之间的差分电压的装置。 钳位电路是用于将预放大器的放大的差分电压钳位在预定义的电压范围之间的装置。 功率放大器是用于增加差分电压信号的功率的装置。 本发明能够在不降低放大器的频率带宽的情况下保持来自运算放大器的快速响应。

公开(公告)号：US06353567B1

公开(公告)日：2002-03-05

申请号：US09684801

申请日：2000-10-06

申请人： Shih-Huang Huang ,  Hsin-Pang Lu

发明人： Shih-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C700

CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C7/067 ,  G11C7/1048

摘要： A data outputting circuit for semiconductor memory device, comprising a pre-charging unit, a data pre-sensing unit made up of a first sense amplifier, a second sense amplifier and an inverter, a data sense amplifier and an output buffer. The data pre-sensing unit is respectively coupled to a position in a first data line having one half loading and a position in a second data line having one half loading. One of the respective signals of the first data line and the second data line is amplified and the other of the respective signals is maintained after passing through the data pre-sensing unit. Thereby, the signal difference between the first data line and the second data line is amplified by means of the data pre-sensing unit and is sufficient to facilitate sensing of the data sense amplifier, even though there exists large loading both in the first data line and the second data line.

摘要翻译： 一种用于半导体存储器件的数据输出电路，包括预充电单元，由第一读出放大器，第二读出放大器和反相器构成的数据预感测单元，数据读出放大器和输出缓冲器。 数据预感测单元分别耦合到具有一个半负载的第一数据线中的位置和具有一个半负载的第二数据线中的位置。 第一数据线和第二数据线的相应信号中的一个被放大，并且在通过数据预感测单元之后保持各个信号中的另一个。 因此，第一数据线和第二数据线之间的信号差异通过数据预感测单元被放大，并且足以便于数据读出放大器的感测，即使在第一数据线中存在大的负载 和第二条数据线。

公开(公告)号：US06304506B1

公开(公告)日：2001-10-16

申请号：US09684116

申请日：2000-10-06

申请人： Shih-Huang Huang ,  Hsin-Pang Lu

发明人： Shih-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/22

摘要： An energy-saving device for a memory circuit. The energy-saving device is capable of immediately terminating a local sense amplifier enable signal to a sense amplifier. The energy-saving device employs a plurality of Schmitt triggering circuits with each Schmitt triggering circuit capable of receiving an operational signal and an inverse operational signal and capable of issuing a Schmitt triggering signal to a data-transmission tester. The data-transmission tester will issue a response signal when change in the Schmitt triggering signal is detected. A data-transition-detected pulse is sent from a data-transmission-testing pulse generation circuit to a power shut down signaling circuit to terminate the local sense amplifier enable signal when the data-transmission-testing pulse-generation circuit receives a response signal.

摘要翻译： 一种用于存储电路的节能装置。 节能装置能够立即将本地读出放大器使能信号终止于读出放大器。 节能装置采用多个施密特触发电路，每个施密特触发电路能够接收操作信号和反向操作信号，并且能够向数据传输测试器发出施密特触发信号。 当检测到施密特触发信号的变化时，数据传输测试仪将发出响应信号。 数据转换检测脉冲从数据传输测试脉冲发生电路发送到电源关闭信号电路，以在数据传输测试脉冲发生电路接收到响应信号时终止本地读出放大器使能信号。

公开(公告)号：US6118731A

公开(公告)日：2000-09-12

申请号：US389817

申请日：1999-09-03

申请人： Shih-Huang Huang ,  Hsin-Pang Lu

发明人： Shih-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1078

摘要： A method is proposed for eliminating signal skew in an SDRAM (Synchronized Dynamic Random-Access Memory) device resulting from the data signal being attenuated into different input signal amplitudes at the respective input points into the memory cells in the SDRAM device. The method is intended for use on a SDRAM device having at least a first memory cell and a second memory cell which are connected to a common signal line which transmits a data signal to both the first and the second memory cells. Due to the data signal being gradually attenuated along the signal line, the input signal amplitudes at the respective input points into the first and second memory cells are different, which would otherwise cause signal skew. In accordance with this method, the trigger voltage levels of the memory cells are adjusted in such a manner as to be substantially equal to the respective input signal amplitudes at a specific trigger time, so that all the memory cells can be triggered substantially concurrently without the occurrence of signal skew. Typically, the trigger voltage levels can be adjusted by adjusting the respective threshold voltages or current gains of the NMOS transistor and PMOS transistor in an inverter used as the I/O buffer of each memory cell. By this method, the adjustment can be easily achieved without having to provide additional circuitry to the SDRAM device. This method is therefore useful in solving the problem of signal skew in the SDRAM device.

摘要翻译： 提出了一种用于消除SDRAM（同步动态随机存取存储器）中的信号偏移的方法，该信号由数据信号衰减到各个输入点处的不同输入信号幅度，进入SDRAM器件中的存储单元。 该方法旨在用于具有至少第一存储器单元和第二存储器单元的SDRAM器件，该第一存储器单元和第二存储器单元连接到向第一和第二存储器单元发送数据信号的公共信号线。 由于数据信号沿着信号线逐渐衰减，所以进入第一和第二存储器单元的各个输入点的输入信号幅度不同，否则会导致信号偏移。 按照这种方法，存储器单元的触发电压电平被调节成基本上等于在特定触发时间的相应输入信号幅度，使得所有的存储单元可以基本同时触发，而没有 出现信号偏移。 通常，可以通过调整用作每个存储单元的I / O缓冲器的反相器中的NMOS晶体管和PMOS晶体管的相应阈值电压或电流增益来调整触发电压电平。 通过这种方法，可以容易地实现调整，而不必向SDRAM设备提供额外的电路。 因此，该方法可用于解决SDRAM器件中的信号偏移问题。

公开(公告)号：US20050097483A1

公开(公告)日：2005-05-05

申请号：US10700459

申请日：2003-11-05

申请人： Hsin-Pang Lu ,  Chung-Hao Cheng

发明人： Hsin-Pang Lu ,  Chung-Hao Cheng

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： Disclosed are a verifier and method for dimension rule check. By checking all basic units in a database and the basic units related to the bulk according to predefined spacing rules, a warning set within the database can be distinguished from those basic units checked by spacing rules. The warning set can specify where or what may be ignored by the spacing rules and should be concerned to refine the spacing rules.

摘要翻译： 公开了一种维度规则检查的验证器和方法。 通过根据预定义的间隔规则检查数据库中的所有基本单位和与批量相关的基本单位，数据库中的警告集可以与通过间隔规则检查的基本单位区分开。 警告集可以指定间隔规则的哪里或什么可以忽略，并且应该关注改进间距规则。

公开(公告)号：US06593645B2

公开(公告)日：2003-07-15

申请号：US09797542

申请日：2001-03-01

申请人： Chian-Gauh Shih ,  Hsin-Pang Lu

发明人： Chian-Gauh Shih ,  Hsin-Pang Lu

IPC分类号： H01L2302

CPC分类号： H01L23/52 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1052 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional system-on-chip structure comprises a plurality of chips and a plurality of plugs respectively fabricated in the chips. The chips are stacked on top of each other and each includes a periphery circuitry region. A plurality of contact pads is fabricated in each of the periphery circuitry regions. The plugs are formed in the corresponding stacked chips, and are electrically connected to the corresponding contact pads of two of the corresponding chips which are adjacent to each other, or two of the corresponding chips which are not adjacent to each other.

摘要翻译： 三维片上系统结构包括分别制造在芯片中的多个芯片和多个插头。 芯片堆叠在彼此的顶部，并且每个芯片包括外围电路区域。 在每个外围电路区域中制造多个接触焊盘。 插头形成在相应的堆叠芯片中，并且电连接到彼此相邻的相应芯片中的两个对应的接触焊盘，或彼此不相邻的相应芯片中的两个。

公开(公告)号：US6130847A

公开(公告)日：2000-10-10

申请号：US358339

申请日：1999-07-21

申请人： Shih-Huang Huang ,  Hsin-Pang Lu

发明人： Shih-Huang Huang ,  Hsin-Pang Lu

IPC分类号： G11C7/12 ,  G11C7/22 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/12

摘要： A semiconductor memory device including a fast write recovery circuit. The semiconductor memory device has a memory array, a sense amplifier and the fast write recovery circuit. Before the end of a precharging operation, a last bit of data is written into a memory cell of the memory by the sense amplifier, as well as by the fast write recovery circuit from the other end. Thus, the time required for writing the last bit of data is shortened to prevent from writing a fragmental data into the memory cell in a transient write cycle. Furthermore, a write operation with a high speed can be executed with being restricted by layout.

摘要翻译： 一种包括快速写入恢复电路的半导体存储器件。 半导体存储器件具有存储器阵列，读出放大器和快速写入恢复电路。 在预充电操作结束之前，由读出放大器以及来自另一端的快速写入恢复电路将最后一位数据写入存储器的存储单元。 因此，写入数据的最后一位所需的时间被缩短以防止在瞬态写入周期中将分段数据写入存储器单元。 此外，可以通过布局限制来执行高速的写入操作。

公开(公告)号：US06967875B2

公开(公告)日：2005-11-22

申请号：US10419223

申请日：2003-04-21

申请人： Chung-Hao Chen ,  Hsin-Pang Lu

发明人： Chung-Hao Chen ,  Hsin-Pang Lu

IPC分类号： G11C11/417 ,  G11C16/04

CPC分类号： G11C11/417

摘要： The memory system includes a plurality of memory cells that are arranged for forming a column, and the plurality of memory cells are coupled with a first bitline and a second bitline individually. Additionally, the memory system further includes a bitline conditioning circuit to perform the pre-charge procedure thereof; and that includes a plurality of wordlines. Furthermore, the memory system further includes a compensating-circuit to keep the voltage that is requirement for the access procedure, wherein the bitline conditioning circuit and the compensating-circuit couple to receive a pair of complemental signals so as to control the interaction between the pre-charge procedure and the compensation procedure from each other.

摘要翻译： 存储器系统包括多个存储单元，其被布置用于形成列，并且多个存储单元分别与第一位线和第二位线耦合。 此外，存储器系统还包括执行其预充电过程的位线调节电路; 并且包括多个字线。 此外，存储系统还包括补偿电路，以保持对接入过程所需的电压，其中位线调理电路和补偿电路耦合以接收一对互补信号，以便控制前置放大器之间的相互作用 充电程序和补偿程序。