摘要:
A data outputting circuit for semiconductor memory device, comprising a pre-charging unit, a data pre-sensing unit made up of a first sense amplifier, a second sense amplifier and an inverter, a data sense amplifier and an output buffer. The data pre-sensing unit is respectively coupled to a position in a first data line having one half loading and a position in a second data line having one half loading. One of the respective signals of the first data line and the second data line is amplified and the other of the respective signals is maintained after passing through the data pre-sensing unit. Thereby, the signal difference between the first data line and the second data line is amplified by means of the data pre-sensing unit and is sufficient to facilitate sensing of the data sense amplifier, even though there exists large loading both in the first data line and the second data line.
摘要:
An energy-saving device for a memory circuit. The energy-saving device is capable of immediately terminating a local sense amplifier enable signal to a sense amplifier. The energy-saving device employs a plurality of Schmitt triggering circuits with each Schmitt triggering circuit capable of receiving an operational signal and an inverse operational signal and capable of issuing a Schmitt triggering signal to a data-transmission tester. The data-transmission tester will issue a response signal when change in the Schmitt triggering signal is detected. A data-transition-detected pulse is sent from a data-transmission-testing pulse generation circuit to a power shut down signaling circuit to terminate the local sense amplifier enable signal when the data-transmission-testing pulse-generation circuit receives a response signal.
摘要:
A sense amplifier can be used with a high-speed IC memory device, which sense amplifier can help reduce the sensing latency during read operations to the memory device so as to allow fast access speed to the memory device. The sense amplifier includes a first-stage circuit, coupled to the bit lines of the memory device, for amplifying the differential data signal on the bit lines. Furthermore, a second-stage circuit has an input side coupled to receive the output signal from the first-stage circuit and an output side coupled to the bit lines, and is used for amplifying the output signal from the first-stage circuit and feeding the amplified signal back to the bit lines. The first-stage circuit and the second-stage circuit in combination constitute a positive feedback amplification loop coupled to the bit lines for amplifying the differential data signal on the bit lines to a detectable level. This positive feedback amplification loop allows the differential data signal on the bit lines to be quickly amplified to the detectable level with a reduced sensing latency, thus increasing the access speed to the associated memory device. Moreover, even though the bit lines are increased in length, the sensing speed is not significantly affected. This feature can also help save circuit layout space.
摘要:
The memory system includes a plurality of memory cells that are arranged for forming a column, and the plurality of memory cells are coupled with a first bitline and a second bitline individually. Additionally, the memory system further includes a bitline conditioning circuit to perform the pre-charge procedure thereof; and that includes a plurality of wordlines. Furthermore, the memory system further includes a compensating-circuit to keep the voltage that is requirement for the access procedure, wherein the bitline conditioning circuit and the compensating-circuit couple to receive a pair of complemental signals so as to control the interaction between the pre-charge procedure and the compensation procedure from each other.
摘要:
A sense/output circuit is designed for use with a memory device, such as an SDRAM (Synchronized Dynamic Random-Access Memory) device, which is capable of switching off some power-consuming circuit components immediately after the requested data output is completed. This feature can help reduce the power consumption by the overall memory system, making the use of the SDRAM device more cost-effective. Moreover, the reduction of power consumption can be achieved without concerning process parameters, component parameters, and temperature variations. As a result, the delay margin can be reduced compared to the prior art, which also contribute to the reduction of power consumption.
摘要:
A voltage regulator capable of improving system response. The voltage regulator includes a feedback circuit and an operational amplifier. The input terminal of the feedback circuit is coupled to an output voltage terminal for attenuating signals coming out of the output terminal. The operational amplifier comprises a pre-amplifier, a clamping circuit and a power amplifier, all serially connected together. The input terminals of the pre-amplifier are respectively coupled to the output terminal of the feedback circuit and an input voltage terminal. The pre-amplifier is a device for amplifying differential voltage between input voltage signals and feedback voltage signals. The clamping circuit is a device for clamping amplified differential voltage from the pre-amplifier between a pre-defined voltage range. The power amplifier is a device for increasing the power of the differential voltage signals. The invention is able to maintain a quick response from the operational amplifier without reducing the frequency bandwidth of the amplifier.
摘要:
A method is proposed for eliminating signal skew in an SDRAM (Synchronized Dynamic Random-Access Memory) device resulting from the data signal being attenuated into different input signal amplitudes at the respective input points into the memory cells in the SDRAM device. The method is intended for use on a SDRAM device having at least a first memory cell and a second memory cell which are connected to a common signal line which transmits a data signal to both the first and the second memory cells. Due to the data signal being gradually attenuated along the signal line, the input signal amplitudes at the respective input points into the first and second memory cells are different, which would otherwise cause signal skew. In accordance with this method, the trigger voltage levels of the memory cells are adjusted in such a manner as to be substantially equal to the respective input signal amplitudes at a specific trigger time, so that all the memory cells can be triggered substantially concurrently without the occurrence of signal skew. Typically, the trigger voltage levels can be adjusted by adjusting the respective threshold voltages or current gains of the NMOS transistor and PMOS transistor in an inverter used as the I/O buffer of each memory cell. By this method, the adjustment can be easily achieved without having to provide additional circuitry to the SDRAM device. This method is therefore useful in solving the problem of signal skew in the SDRAM device.
摘要:
A sense amplifier circuit for a semiconductor memory device. The sense amplifier of this invention has four more NMOS transistors than a conventional amplifier. The gate terminals of two of the NMOS transistors are connected to a write enable line. The gate terminals of the other two NMOS transistors are connected to a first and a second node point, which are in turn connected to a bit line and a complementary bit line, respectively. Through a feedback circuit provided by these four additional NMOS transistors, two of the NMOS transistors are switched on during a write cycle to provide a ground connection so that voltage level of the sense amplifier is rapidly pulled down. Since the latching speed of the sense amplifier is increased, the operating speed of the memory is increased, as well. In addition, partial writing of data can be avoided.
摘要:
A reference generating apparatus and a sampling apparatus thereof are provided. The coding module is configured to code and decode a first reference signal to retrieve a second reference signal with less power than generating the first reference signal. The second reference signal is identical to the first reference signal in amplitude.
摘要:
Disclosed are a verifier and method for dimension rule check. By checking all basic units in a database and the basic units related to the bulk according to predefined spacing rules, a warning set within the database can be distinguished from those basic units checked by spacing rules. The warning set can specify where or what may be ignored by the spacing rules and should be concerned to refine the spacing rules.