发明授权
US6037211A Method of fabricating contact holes in high density integrated circuits
using polysilicon landing plug and self-aligned etching processes
失效
使用多晶硅着陆塞和自对准蚀刻工艺在高密度集成电路中制造接触孔的方法
- 专利标题： Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes
- 专利标题（中）： 使用多晶硅着陆塞和自对准蚀刻工艺在高密度集成电路中制造接触孔的方法
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申请号： US841836申请日： 1997-05-05
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公开(公告)号： US6037211A公开(公告)日： 2000-03-14
- 发明人: Erik S. Jeng , Yue-Feng Chen , Bi-Ling Chen
- 申请人： Erik S. Jeng , Yue-Feng Chen , Bi-Ling Chen
- 申请人地址： TWX
- 专利权人： Vanguard International Semiconductor Corporation
- 当前专利权人： Vanguard International Semiconductor Corporation
- 当前专利权人地址： TWX
- 主分类号： H01L21/60
- IPC分类号： H01L21/60 ; H01L21/768 ; H01L21/8242 ; H01L21/28 ; H01L21/336
摘要：
A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate structure, polysilicon hard masks and polysilicon spacers are used as etching masks in a self-aligned contact process. In addition, the landing plugs incorporate the polysilicon spacers as part of landing plug to increase the contact area. As a result, wide contact processing windows can be achieved in high density integrated circuits.
公开/授权文献
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