发明授权
US6041390A Token mechanism for cache-line replacement within a cache memory having
redundant cache lines
失效
具有冗余高速缓存线的高速缓冲存储器内的缓存线替换的令牌机制
- 专利标题: Token mechanism for cache-line replacement within a cache memory having redundant cache lines
- 专利标题(中): 具有冗余高速缓存线的高速缓冲存储器内的缓存线替换的令牌机制
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申请号: US773545申请日: 1996-12-23
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公开(公告)号: US6041390A公开(公告)日: 2000-03-21
- 发明人: Peichun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Steve Tung
- 申请人: Peichun Peter Liu , Rajinder Paul Singh , Shih-Hsiung Steve Tung
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: G06F12/12
- IPC分类号: G06F12/12
摘要:
A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated. Each token register also has a bypass circuit. A bypass circuit is utilized to transfer the token from one token register to an adjacent token circuit in response to an indication from the associated allocation-indicating circuit.
公开/授权文献
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