An integrated circuit which includes a first transistor device portion having an N+ doped region drain terminal in an N- well in a P- substrate, an N+ doped region source terminal in the P- substrate, and a gate separated from the source and drain regions by a layer of silicon dioxide; and a second transistor device portion including an N+ doped region drain terminal in the P- substrate, an N+ doped region source terminal in the P- substrate, and a gate separated from the source and drain regions by a layer of silicon dioxide; conductive means connecting the drain region of the first transistor device portion to a node to be discharged, a conductor connecting the gate of the first transistor device portion to a source of biasing potential equal to the source voltage used in a low voltage process, another conductor connecting the source of the second transistor device portion to a source of ground potential; and a third conductor for providing a source of positive input potential to the gate terminal of the second transistor device portion. The enabling of the second transistor device portion enables the first transistor device portion and discharges the node without causing breakdown of the silicon dioxide layers or any junction of the first and the second transistor device portions because the large N well distributes the high voltage over a number of junctions so that no junction sees a breakdown voltage.