发明授权
US6043675A Logic circuit utilizing capacitive coupling, an AD converter and a DA
converter
失效
使用电容耦合的逻辑电路,AD转换器和DA转换器
- 专利标题: Logic circuit utilizing capacitive coupling, an AD converter and a DA converter
- 专利标题(中): 使用电容耦合的逻辑电路,AD转换器和DA转换器
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申请号: US888900申请日: 1997-07-07
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公开(公告)号: US6043675A公开(公告)日: 2000-03-28
- 发明人: Yoshihiro Miyamoto
- 申请人: Yoshihiro Miyamoto
- 申请人地址: JPX Kanagawa
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JPX Kanagawa
- 优先权: JPX9-016968 19970130; JPX9-063344 19970317
- 主分类号: H03M1/44
- IPC分类号: H03M1/44 ; G06F7/50 ; H03K5/08 ; H03K19/08 ; H03K19/23 ; H03M1/12 ; H03M1/14 ; H03M1/40 ; H03M1/42 ; H03M1/46 ; H03M1/60 ; H03M1/66 ; H03M1/68 ; H03M1/74 ; H03K19/20
摘要:
According to the present invention, various logic circuits, AD converters, DA converters and counter circuits can be constituted with a small number of transistors by employing a capacitive coupling circuit. An analog/digital converter comprises: an input terminal, for which analog input is provided; an output terminal of N (N is a plural number) bits, for which binary output is provided; and N unit circuits arranged in parallel, each including an input capacitor having one electrode connected to the input terminal, a first inverter connected to the other electrode of the input capacitor, and a second inverter connected to the first inverter, wherein outputs of the second inverters of the unit circuits are respectively provided for the output terminals, wherein inverted outputs of the outputs for the unit circuits are fed back via feedback capacitors to respective input terminals of the first inverters of the unit circuits corresponding to lower bits, and wherein a capacitance of the feedback capacitor, which corresponds to the inverted output of the M-th (M is an integer) unit circuit from the most significant bit, is 1/2.sup.M times a capacitance of the input capacitor of the unit circuit that is fed back.
公开/授权文献
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